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| v6.0 40MX and 42MX FPGA Families Features High Capacity * * * * * Single-Chip ASIC Alternative 3,000 to 54,000 System Gates Up to 2.5 kbits Configurable Dual-Port SRAM Fast Wide-Decode Circuitry Up to 202 User-Programmable I/O Pins HiRel Features * * * * Commercial, Industrial, Automotive, and Military Temperature Plastic Packages Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages QML Certification Ceramic Devices Available to DSCC SMD Ease of Integration * * * * * * Mixed-Voltage Operation (5.0V or 3.3V for core and I/Os), with PCI-Compliant I/Os Up to 100% Resource Utilization and 100% Pin Locking Deterministic, User-Controllable Timing Unique In-System Diagnostic and Verification Capability with Silicon Explorer II Low Power Consumption IEEE Standard 1149.1 (JTAG) Boundary Scan Testing High Performance * * * * * 5.6 ns Clock-to-Out 250 MHz Performance 5 ns Dual-Port SRAM Access 100 MHz FIFOs 7.5 ns 35-Bit Address Decode Product Profile Device Capacity System Gates SRAM Bits Logic Modules Sequential Combinatorial Decode Clock-to-Out SRAM Modules (64x4 or 32x8) Dedicated Flip-Flops Maximum Flip-Flops Clocks User I/O (maximum) PCI Boundary Scan Test (BST) Packages (by pin count) PLCC PQFP VQFP TQFP CQFP PBGA A40MX02 3,000 - - 295 - 9.5 ns - - 147 1 57 - - 44, 68 100 80 - - - A40MX04 6,000 - - 547 - 9.5 ns - - 273 1 69 - - 44, 68, 84 100 80 - - - A42MX09 14,000 - 348 336 - 5.6 ns - 348 516 2 104 - - 84 100, 160 100 176 - - A42MX16 24,000 - 624 608 - 6.1 ns - 624 928 2 140 - - 84 100, 160, 208 100 176 - - A42MX24 36,000 - 954 912 24 6.1 ns - 954 1,410 2 176 Yes Yes 84 160, 208 - 176 - - A42MX36 54,000 2,560 1,230 1,184 24 6.3 ns 10 1,230 1,822 6 202 Yes Yes - 208, 240 - - 208, 256 272 January 2004 (c) 2004 Actel Corporation i See the Actel website (www.actel.com) for the latest version of this datasheet. 40MX and 42MX FPGA Families Ordering Information A42MX16 _ 1 PQ 100 ES Application (Temperature Range) Blank = Commercial (0 to +70C) I = Industrial (-40 to +85C) M = Military (-55 to +125C) B = MIL-STD-883 A = Automotive (-40 to +125C) Package Lead Count Package Type PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flat Pack TQ = Thin (1.4 mm) Quad Flat Pack VQ = Very Thin (1.0 mm) Quad Flat Pack BG = Plastic Ball Grid Array CQ = Ceramic Quad Flat Pack Speed Grade Blank = Standard Speed -1 = Approximately 15% Faster than Standard -2 = Approximately 25% Faster than Standard -3 = Approximately 35% Faster than Standard -F = Approximately 40% Slower than Standard Part Number A40MX02 = 3,000 System Gates A40MX04 = 6,000 System Gates A42MX09 = 14,000 System Gates A42MX16 = 24,000 System Gates A42MX24 = 36,000 System Gates A42MX36 = 54,000 System Gates Plastic Device Resources User I/Os Device A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 PLCC 44-Pin 34 34 - - - - PLCC 68-Pin 57 57 - - - - PLCC 84-Pin - 69 72 72 72 - PQFP PQFP PQFP PQFP 100-Pin 160-Pin 208-Pin 240-Pin 57 69 83 83 - - - - 101 125 125 - - - - 140 176 176 - - - - - 202 VQFP 80-Pin 57 69 - - - - VQFP TQFP PBGA 100-Pin 176-Pin 272-Pin - - 83 83 - - - - 104 140 150 - - - - - - 202 Note: Package Definitions PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack, PBGA = Plastic Ball Grid Array ii v6.0 40MX and 42MX FPGA Families Ceramic Device Resources User I/Os Device A42MX36 Note: Package Definitions CQFP 208-Pin 176 CQFP 256-Pin 202 CQFP = Ceramic Quad Flat Pack Temperature Grade Offerings Package PLCC 44 PLCC 68 PLCC 84 PQFP 100 PQFP 160 PQFP 208 PQFP 240 VQFP 80 VQFP 100 TQFP 176 PBGA 272 CQFP 208 CQFP 256 Note: C = Commercial I = Industrial A = Automotive M = Military B = MIL-STD-883 Class B C, I, A, M C, I, A, M C, I, A, M C, I, A, M C, I, A, M C, I, A, M C, I, A, M C, I, M C, M, B C, M, B C, I, A, M A40MX02 C, I, M C, I, A, M A40MX04 C, I, M C, I, M C, I, A, M C, I, A, M C, I, A, M C, I, A, M C, I, A, M C, I, M C, I, M C, I, M C, I, A, M C, I, A, M C, I, A, M C, I, A, M C, I, A, M C, I, M A42MX09 A42MX16 A42MX24 A42MX36 Speed Grade Offerings -F C I A M B Std -1 -2 -3 Note: Refer to the 40MX and 42MX Automotive Family FPGAs datasheet for details on automotive-grade MX offerings. Contact your local Actel representative for device availability. v6.0 iii 40MX and 42MX FPGA Families Table of Contents 40MX and 42MX FPGA Families General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 MX Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 5.0V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 5V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 3.3V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 3.3V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Mixed 5.0V/3.3V Operating Conditions (for 42MX Devices Only) . . . . . . . . . . . . . 1-18 Mixed 5.0V/3.3V Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 Output Drive Characteristics for 5.0V PCI Signaling . . . . . . . . . . . . . . . . . . . . . . . . 1-19 Output Drive Characteristics for 3.3V PCI Signaling . . . . . . . . . . . . . . . . . . . . . . . . 1-20 Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 Sequential Module Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 Sequential Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 Decode Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 SRAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 Dual-Port SRAM Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 Predictable Performance: Tight Delay Distributions . . . . . . . . . . . . . . . . . . . . . . . 1-30 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 PCI System Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35 PCI Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-77 Package Pin Assignments 44-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 84-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 v6.0 v 40MX and 42MX FPGA Families Table of Contents 100-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 160-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 208-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 240-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 80-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 100-Pin VQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 176-Pin TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 256-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 272-Pin BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 vi v6.0 40MX and 42MX FPGA Families 40MX and 42MX FPGA Families General Description Actel's 40MX and 42MX families offer a cost-effective design solution at 5V. The MX devices are single-chip solutions and provide high performance while shortening the system design and development cycle. MX devices can integrate and consolidate logic implemented in multiple PALs, CPLDs, and FPGAs. Example applications include high-speed controllers and address decoding, peripheral bus interfaces, DSP, and coprocessor functions. The MX device architecture is based on Actel's patented antifuse technology implemented in a 0.45m triplemetal CMOS process. With capacities ranging from 3,000 to 54,000 system gates, the MX devices provide performance up to 250 MHz, are live on power-up and have one-fifth the standby power consumption of comparable FPGAs. Actel's MX FPGAs provide up to 202 user I/Os and are available in a wide variety of packages and speed grades. Actel's A42MX24 and A42MX36 devices also feature MultiPlex I/Os, which support mixed-voltage systems, enable programmable PCI, deliver high-performance operation at both 5.0V and 3.3V, and provide a lowpower mode. The devices are fully compliant with the PCI Local Bus Specification (version 2.1). They deliver 200 MHz on-chip operation and 6.1 ns clock-to-output performance. The 42MX24 and 42MX36 devices include system-level features such as IEEE Standard 1149.1 (JTAG) Boundary Scan Testing and fast wide-decode modules. In addition, the A42MX36 device offers dual-port SRAM for implementing fast FIFOs, LIFOs, and temporary data storage. The storage elements can efficiently address applications requiring wide datapath manipulation and can perform transformation functions such as those required for telecommunications, networking, and DSP. All MX devices are fully tested over automotive and military temperature ranges. In addition, the largest member of the family, the A42MX36, is available in both CQ208 and CQ256 ceramic packages screened to MILSTD-883 levels. For easy prototyping and conversion from plastic to ceramic, the CQ208 and PQ208 devices are pincompatible. MX Architectural Overview The MX devices are composed of fine-grained building blocks that enable fast, efficient logic designs. All devices within these families are composed of logic modules, I/O modules, routing resources and clock networks, which are the building blocks for fast logic designs. In addition, the A42MX36 device contains embedded dual-port SRAM modules, which are optimized for high-speed datapath functions such as FIFOs, LIFOs and scratchpad memory. A42MX24 and A42MX36 also contain widedecode modules. Logic Modules The 40MX logic module is an eight-input, one-output logic circuit designed to implement a wide range of logic functions with efficient use of interconnect routing resources (Figure 1-1). The logic module can implement the four basic logic functions (NAND, AND, OR and NOR) in gates of two, three, or four inputs. The logic module can also implement a variety of D-latches, exclusivity functions, AND-ORs and OR-ANDs. No dedicated hard-wired latches or flip-flops are required in the array; latches and flipflops can be constructed from logic modules whenever required in the application. Figure 1-1 * 40MX Logic Module v6.0 1-1 40MX and 42MX FPGA Families The 42MX devices contain three types of logic modules: combinatorial (C-modules), sequential (S-modules) and decode (D-modules). Figure 1-2 illustrates the combinatorial logic module. The S-module, shown in Figure 1-3, implements the same combinatorial logic function as the C-module while adding a sequential element. The sequential element can be configured as either a D-flip-flop or a transparent latch. The S-module register can be bypassed so that it implements purely combinatorial logic. A0 B0 D00 D01 D10 D11 S1 A1 B1 Y S0 Figure 1-2 * 42MX C-Module Implementation D00 D01 D10 D11 S1 S0 Y D CLR Q OUT D00 D01 D10 D11 S1 S0 Y D GATE Q OUT Up to 7-Input Function Plus D-Type Flip-Flop with Clear Up to 7-Input Function Plus Latch D00 D0 Y D1 S D GATE CLR Q OUT D01 D10 D11 S1 S0 Y OUT Up to 4-Input Function Plus Latch with Clear Up to 8-Input Function (Same as C-Module) Figure 1-3 * 42MX S-Module Implementation 1 -2 v6.0 40MX and 42MX FPGA Families A42MX24 and A42MX36 devices contain D-modules, which are arranged around the periphery of the device. D-modules contain wide-decode circuitry, providing a fast, wide-input AND function similar to that found in CPLD architectures (Figure 1-4). The D-module allows A42MX24 and A42MX36 devices to perform widedecode functions at speeds comparable to CPLDs and PALs. The output of the D-module has a programmable inverter for active HIGH or LOW assertion. The D-module output is hardwired to an output pin, and can also be fed back into the array to be incorporated into other logic. highest order address bits (RDAD5 and WRAD5) are not used. The read and write ports of the SRAM block contain independent clocks (RCLK and WCLK) with programmable polarities offering active HIGH or LOW implementation. The SRAM block contains eight data inputs (WD[7:0]), and eight outputs (RD[7:0]), which are connected to segmented vertical routing tracks. The A42MX36 dual-port SRAM blocks provide an optimal solution for high-speed buffered applications requiring FIFO and LIFO queues. The ACTgen Macro Builder within Actel's Designer software provides capability to quickly design memory functions with the SRAM blocks. Unused SRAM blocks can be used to implement registers for other user logic within the design. 7 Inputs Hard-Wire to I/O Programmable Inverter Feedback to Array Figure 1-4 * A42MX24 and A42MX36 D-Module Implementation Dual-Port SRAM Modules The A42MX36 device contains dual-port SRAM modules that have been optimized for synchronous or asynchronous applications. The SRAM modules are arranged in 256-bit blocks that can be configured as 32x8 or 64x4. SRAM modules can be cascaded together to form memory spaces of user-definable width and depth. A block diagram of the A42MX36 dual-port SRAM block is shown in Figure 1-5. The A42MX36 SRAM modules are true dual-port structures containing independent read and write ports. Each SRAM module contains six bits of read and write addressing (RDAD[5:0] and WRAD[5:0], respectively) for 64x4-bit blocks. When configured in byte mode, the WD[7:0] Latches [7:0] WRAD[5:0] [5:0] Latches Write Port Logic SRAM Module 32 x 8 or 64 x 4 (256 Bits) [5:0] Read Port Logic Latches Read Logic RDAD[5:0] REN RCLK MODE BLKEN WEN WCLK Write Logic RD[7:0] Routing Tracks Figure 1-5 * A42MX36 Dual-Port SRAM Block v6.0 1-3 40MX and 42MX FPGA Families Routing Structure The MX architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O modules. These routing tracks are metal interconnects that may be continuous or split into segments. Varying segment lengths allow the interconnect of over 90% of design tracks to occur with only two antifuse connections. Segments can be joined together at the ends using antifuses to increase their lengths up to the full length of the track. All interconnects can be accomplished with a maximum of four antifuses. Segmented Horizontal Routing Logic Modules Antifuses Vertical Routing Tracks Horizontal Routing Horizontal routing tracks span the whole row length or are divided into multiple segments and are located in between the rows of modules. Any segment that spans more than one-third of the row length is considered a long horizontal segment. A typical channel is shown in Figure 1-6. Within horizontal routing, dedicated routing tracks are used for global clock networks and for power and ground tie-off tracks. Non-dedicated tracks are used for signal nets. Figure 1-6 * MX Routing Structure Clock Networks The 40MX devices have one global clock distribution network (CLK). A signal can be put on the CLK network by being routed through the CLKBUF buffer. In 42MX devices, there are two low-skew, high-fanout clock distribution networks, referred to as CLKA and CLKB. Each network has a clock module (CLKMOD) that can select the source of the clock signal from any of the following (Figure 1-7 on page 1-5): * * * * Externally from the CLKA pad, using CLKBUF buffer Externally from the CLKB pad, using CLKBUF buffer Internally from the CLKINTA input, using CLKINT buffer Internally from the CLKINTB input, using CLKINT buffer Vertical Routing Another set of routing tracks run vertically through the module. There are three types of vertical tracks: input, output, and long. Long tracks span the column length of the module, and can be divided into multiple segments. Each segment in an input track is dedicated to the input of a particular module; each segment in an output track is dedicated to the output of a particular module. Long segments are uncommitted and can be assigned during routing. Each output segment spans four channels (two above and two below), except near the top and bottom of the array, where edge effects occur. Long vertical tracks contain either one or two segments. An example of vertical routing tracks and segments is shown in Figure 1-6. The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal clock track are located in each horizontal routing channel. Clock input pads in both 40MX and 42MX devices can also be used as normal I/Os, bypassing the clock networks. The A42MX36 device has four additional register control resources, called quadrant clock networks (Figure 1-8 on page 1-5). Each quadrant clock provides a local, highfanout resource to the contiguous logic modules within its quadrant of the device. Quadrant clock signals can originate from specific I/O pins or from the internal array and can be used as a secondary register clock, register clear, or output enable. Antifuse Structures An antifuse is a "normally open" structure. The use of antifuses to implement a programmable logic device results in highly testable structures as well as efficient programming algorithms. There are no pre-existing connections; temporary connections can be made using pass transistors. These temporary connections can isolate individual antifuses to be programmed and individual circuit structures to be tested, which can be done before and after programming. For instance, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified. 1 -4 v6.0 40MX and 42MX FPGA Families CLKB CLKA From Pads CLKINB CLKINA CLKMOD S0 S1 Internal Signal CLKO(17) Clock Drivers CLKO(16) CLKO(15) CLKO(2) CLKO(1) Clock Tracks Figure 1-7 * Clock Networks of 42MX Devices QCLKA Quad Clock Modul QCLK1 QCLK3 Quad Clock Modul QCLKC QCLKD *QCLK3IN S0 S1 S1 S0 QCLKB *QCLK1IN Quad Clock Modul *QCLK2IN S0 S1 QCLK2 QCLK4 Quad Clock Modul *QCLK4IN S1 S0 Note: *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals. Figure 1-8 * Quadrant Clock Network of A42MX36 Devices v6.0 1-5 40MX and 42MX FPGA Families MultiPlex I/O Modules 42MX devices feature Multiplex I/Os and support 5.0V, 3.3V, and mixed 3.3V/5.0V operations. The MultiPlex I/O modules provide the interface between the device pins and the logic array. Figure 1-9 is a block diagram of the 42MX I/O module. A variety of user functions, determined by a library macro selection, can be implemented in the module. (Refer to the Antifuse Macro Library Guide for more information.) All 42MX I/O modules contain tristate buffers, with input and output latches that can be configured for input, output, or bidirectional operation. All 42MX devices contain flexible I/O structures, where each output pin has a dedicated output-enable control (Figure 1-9). The I/O module can be used to latch input or output data, or both, providing fast set-up time. In addition, the Actel Designer software tools can build a Dtype flip-flop using a C-module combined with an I/O module to register input and output signals. Refer to the Antifuse Macro Library Guide for more details. A42MX24 and A42MX36 devices also offer selectable PCI output drives, enabling 100% compliance with version 2.1 of the PCI specification. For low-power systems, all inputs and outputs are turned off to reduce current consumption to below 500A. To achieve 5.0V or 3.3V PCI-compliant output drives on A42MX24 and A42MX36 devices, a chip-wide PCI fuse is programmed via the Device Selection Wizard in the Designer software (Figure 1-10). When the PCI fuse is not programmed, the output drive is standard. Actel's Designer software development tools provide a design library of I/O macro functions that can implement all I/O configurations supported by the MX FPGAs. EN STD Signal Output PCI Drive PCI Enable Fuse Figure 1-10 * PCI Output Structure of A42MX24 and A42MX36 Devices Other Architectural Features Performance MX devices can operate with internal clock frequencies of 250 MHz, enabling fast execution of complex logic functions. MX devices are live on power-up and do not require auxiliary configuration devices and thus are an optimal platform to integrate the functionality contained in multiple programmable logic devices. In addition, designs that previously would have required a gate array to meet performance can be integrated into an MX device with improvements in cost and time-tomarket. Using timing-driven place-and-route (TDPR) tools, designers can achieve highly deterministic device performance. User Security The Actel FuseLock provides robust security against design theft. Special security fuses are hidden in the fabric of the device and prevent unauthorized users from accessing the programming and/or probe interfaces. It is virtually impossible to identify or bypass these fuses without damaging the device, making Actel antifuse FPGAs immune to both invasive and noninvasive attacks. Special security fuses in 40MX devices include the Probe Fuse and Program Fuse. The former disables the probing circuitry while the latter prohibits further programming of all fuses, including the Probe Fuse. In 42MX devices, there is the Security Fuse which, when programmed, both disables the probing circuitry and prohibits further programming of the device. Look for this symbol to ensure your valuable IP is secure. For more information, refer to Actel's Implementation of Security in Actel Antifuse FPGAs application note. Q From Array D PAD G/CLK* To Array Q D G/CLK* Note: *Can be configured as a Latch or D Flip-Flop (Using C-Module) Figure 1-9 * 42MX I/O Module 1 -6 v6.0 40MX and 42MX FPGA Families TM ue nonprogrammed), Silicon Sculptor II also allows self-test to verify its own hardware extensively. The procedure for programming an MX device using Silicon Sculptor II is as follows: 1. Load the .AFM file 2. Select the device to be programmed 3. Begin programming When the design is ready to go to production, Actel offers device volume-programming services either through distribution partners or via In-House Programming from the factory. For more details on programming MX devices, please refer to the Programming Antifuse Devices and the Silicon Sculptor II user's guides. Figure 1-11 * Fuselock Programming Device programming is supported through the Silicon Sculptor series of programmers. Silicon Sculptor II is a compact, robust, single-site and multi-site device programmer for the PC. With standalone software, Silicon Sculptor II is designed to allow concurrent programming of multiple units from the same PC. Silicon Sculptor II programs devices independently to achieve the fastest programming times possible. After being programmed, each fuse is verified to insure that it has been programmed correctly. Furthermore, at the end of programming, there are integrity tests that are run to ensure no extra fuses have been programmed. Not only does it test fuses (both programmed and Table 1 * Device 40MX Voltage Support of MX Devices VCC 5.0V 3.3V 42MX - - - VCCA - - 5.0V 3.3V 5.0V VCCI - - 5.0V 3.3V 3.3V Power Supply MX devices are designed to operate in both 5.0V and 3.3V environments. In particular, 42MX devices can operate in mixed 5.0V/3.3V systems. Table 1 describes the voltage support of MX devices. Maximum Input Tolerance 5.5V 3.6V 5.5V 3.6V 5.5V Nominal Output Voltage 5.0V 3.3V 5.0V 3.3V 3.3V Power-Up/Down in Mixed-Voltage Mode When powering up 42MX in mixed voltage mode (VCCA = 5.0V and VCCI = 3.3V), VCCA must be greater than or equal to VCCI throughout the power-up sequence. If VCCI exceeds VCCA during power up, either the I/Os' input protection junction on the I/Os will be forward-biased or the I/Os will be at logical HIGH, and ICC rises to high levels. For power-down, any sequence with VCCA and VCCI can be implemented. Low Power Mode 42MX devices have been designed with a Low Power Mode. This feature, activated with setting the special LP pin to HIGH for a period longer than 800 ns, is particularly useful for battery-operated systems where battery life is a primary concern. In this mode, the core of the device is turned off and the device consumes minimal power with low standby current. In addition, all input buffers are turned off, and all outputs and bidirectional buffers are tristated. Since the core of the device is turned off, the states of the registers are lost. The device must be re-initialized when exiting Low Power Mode. I/ Os can be driven during LP mode, and clock pins should be driven HIGH or LOW and should not float to avoid drawing current. To exit LP mode, the LP pin must be pulled LOW for over 200 s to allow for charge pumps to power up, and device initialization will begin. v6.0 1-7 40MX and 42MX FPGA Families Power Dissipation The general power consumption of MX devices is made up of static and dynamic power and can be expressed with the following equation: The power dissipated by a CMOS circuit can be expressed by the equation: Power (W) = CEQ * VCCA2 * F(1) where: CEQ =Equivalent capacitance expressed in picofarads (pF) VCCA =Power supply in volts (V) F =Switching frequency in megahertz (MHz) General Power Equation P = [ICCstandby + ICCactive] * VCCI + IOL* VOL* N + IOH * (VCCI - VOH) * M where: ICCstandby is the current flowing when no inputs or outputs are changing. ICCactive is the current flowing due to CMOS switching. IOL, IOH are TTL sink/source currents. VOL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. Accurate values for N and M are difficult to determine because they depend on the family type, on design details, and on the system I/O. The power can be divided into two components: static and active. Equivalent Capacitance Equivalent capacitance is calculated by measuring ICCactive at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency-independent, so the results can be used over a wide range of operating conditions. Equivalent capacitance values are shown below. CEQ Values for Actel MX FPGAs Modules (CEQM)3.5 Input Buffers (CEQI)6.9 Output Buffers (CEQO)18.2 Routed Array Clock Buffer Loads (CEQCR)1.4 To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. The equation below shows a piece-wise linear summation over all components. Power = VCCA2 * [(m x CEQM * fm)Modules + (n * CEQI * fn)Inputs + (p * (CEQO + CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 (2) Static Power Component The static power due to standby current is typically a small component of the overall power consumption. Standby power is calculated for commercial, worst-case conditions. The static power dissipation by TTL loads depends on the number of outputs driving, and on the DC load current. For instance, a 32-bit bus sinking 4mA at 0.33V will generate 42mW with all outputs driving LOW, and 140mW with all outputs driving HIGH. The actual dissipation will average somewhere in between, as I/Os switch states with time. where: m = Number of frequency fm = Number of frequency fn = Number of frequency fp logic input output modules buffers buffers switching switching switching at at at Active Power Component Power dissipation in CMOS devices is usually dominated by the dynamic power dissipation. Dynamic power consumption is frequency-dependent and is a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitances due to PC board traces and load device inputs. An additional component of the active power dissipation is the totem pole current in the CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. n p q1 q2 r1 r2 = Number of clock loads on the first routed array clock = Number of clock loads on the second routed array clock = Fixed capacitance due to first routed array clock = Fixed capacitance due to second routed array clock 1 -8 v6.0 40MX and 42MX FPGA Families CEQM = Equivalent capacitance of logic modules in pF CEQI = Equivalent capacitance of input buffers in pF CEQO = Equivalent capacitance of output buffers in pF CEQCR = Equivalent capacitance of routed array clock in pF CL fm fn fp fq1 fq2 = Output load capacitance in pF = Average logic module switching rate in MHz = Average input buffer switching rate in MHz = Average output buffer switching rate in MHz = Average first routed array clock rate in MHz = Average second routed array clock rate in MHz r1 routed_Clk1 41.4 68.6 118 165 185 220 r2 routed_Clk2 N/A N/A 118 165 185 220 resources. Silicon Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the debug cycle and providing a true representation of the device under actual functional situations. Silicon Explorer II samples data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II attaches to a PC's standard COM port, turning the PC into a fully functional 18-channel logic analyzer. Silicon Explorer II allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to a few seconds. Silicon Explorer II is used to control the MODE, DCLK, SDI and SDO pins in MX devices to select the desired nets for debugging. The user simply assigns the selected internal nets in the Silicon Explorer II software to the PRA/PRB output pins for observation. Probing functionality is activated when the MODE pin is held HIGH. Figure 1-12 illustrates the interconnection between Silicon Explorer II and 40MX devices, while Figure 1-13 on page 1-10 illustrates the interconnection between Silicon Explorer II and 42MX devices To allow for probing capabilities, the security fuses must not be programmed. (Refer to Fixed Capacitance Values for MX FPGAs (pF) Device Type A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 Test Circuitry and Silicon Explorer II Probe MX devices contain probing circuitry that provides builtin access to every node in a design, via the use of Silicon Explorer II. Silicon Explorer II is an integrated hardware and software solution that, in conjunction with the Designer software, allow users to examine any of the internal nets of the device while it is operating in a prototyping or a production system. The user can probe into an MX device without changing the placement and routing of the design and without using any additional 16 Logic Analyzer Channels Serial Connection to Windows PC 40MX Silicon Explorer II MODE SDI DCLK SDO PRA PRB Figure 1-12 * Silicon Explorer II Setup with 40MX v6.0 1-9 40MX and 42MX FPGA Families 16 Logic Analyzer Channels Serial Connection to Windows PC 42MX Silicon Explorer II MODE SDI DCLK SDO PRA PRB Figure 1-13 * Silicon Explorer II Setup with 42MX Table 2 * Device Configuration Options for Probe Capability MODE LOW HIGH - PRA, PRB1 User I/Os2 Probe Circuit Outputs Probe Circuit Secured SDI, SDO, DCLK1 User I/Os2 Probe Circuit Inputs Probe Circuit Secured Security Fuse(s) Programmed No No Yes Notes: 1. Avoid using SDI, SDO, DCLK, PRA and PRB pins as input or bidirectional ports. Since these pins are active during probing, input signals will not pass through these pins and may cause contention. 2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. See the Design Consideration It is recommended to use a series 70 termination resistor on every probe connector (SDI, SDO, MODE, DCLK, PRA and PRB). The 70 series termination is used to prevent data transmission corruption during probing and reading back the checksum. Each test section is accessed through the TAP, which has four associated pins: TCK (test clock input), TDI and TDO (test data input and output), and TMS (test mode selector). The TAP controller is a four-bit state machine. The '1's and '0's represent the values that must be present at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state. The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for five TCK cycles. 42MX24 and 42MX36 devices support three types of test data registers: bypass, device identification, and boundary scan. The bypass register is selected when no other register needs to be accessed in a device. This speeds up test data transfer to other devices in a test data path. The 32-bit device identification register is a shift register with four fields (lowest significant byte (LSB), ID number, part number and version). The boundary-scan register observes and controls the state of each I/O pin. IEEE Standard 1149.1 Boundary Scan Test (BST) Circuitry 42MX24 and 42MX36 devices are compatible with IEEE Standard 1149.1 (informally known as Joint Testing Action Group Standard or JTAG), which defines a set of hardware architecture and mechanisms for cost-effective board-level testing. The basic MX boundary-scan logic circuit is composed of the TAP (test access port), TAP controller, test data registers and instruction register (Figure 1-14 on page 1-11). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/ PRELOAD and BYPASS) and some optional instructions. Table 3 on page 1-11 describes the ports that control JTAG testing, while Table 4 on page 1-11 describes the test instructions supported by these MX devices. 1 -1 0 v6.0 40MX and 42MX FPGA Families Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin. The serial pins are used to serially connect all the boundary-scan register cells in a device into a boundaryscan register chain, which starts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic tile and the input, output and control ports of an I/O buffer to capture and load data into the register to control or observe the logic state of each I/O. Boundary Scan Register Bypass Register Control Logic JTAG TMS TCK JTAG TDI Instruction Register TAP Controller Instruction Decode Output MUX TDO Figure 1-14 * 42MX IEEE 1149.1 Boundary Scan Circuitry Table 3 * Port TMS (Test Select) Test Access Port Descriptions Description Mode Serial input for the test logic control bits. Data is captured on the rising edge of the test logic clock (TCK). TCK (Test Clock Input) Dedicated test logic clock used serially to shift test instruction, test data, and control inputs on the rising edge of the clock, and serially to shift the output data on the falling edge of the clock. The maximum clock frequency for TCK is 20 MHz. TDI (Test Data Input) TDO (Test Output) Table 4 * Instruction EXTEST Serial input for instruction and test data. Data is captured on the rising edge of the test logic clock. Data Serial output for test instruction and data from the test logic. TDO is set to an Inactive Drive state (high impedance) when data scanning is not in progress. Supported BST Public Instructions IR Code (IR2.IR0) 000 Instruction Type Mandatory Description Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Allows a snapshot of the signals at the device pins to be captured and examined during operation Tristates all I/Os to allow external signals to drive pins. Please refer to the IEEE Standard 1149.1 specification. Allows state of signals driven from component pins to be determined from the Boundary-Scan Register. Please refer to the IEEE Standard 1149.1 specification for details. Enables the bypass register between the TDI and TDO pins. The test data passes through the selected device to adjacent devices in the test chain. SAMPLE/PRELOAD HIGH Z CLAMP 001 101 110 Mandatory Optional Optional BYPASS 111 Mandatory v6.0 1-11 40MX and 42MX FPGA Families JTAG Mode Activation The JTAG test logic circuit is activated in the Designer software by selecting Tools -> Device Selection. This brings up the Device Selection dialog box as shown in Figure 1-15. The JTAG test logic circuit can be enabled by clicking the "Reserve JTAG Pins" check box. Table 5 explains the pins' behavior in either mode. Figure 1-15 * Device Selection Wizard Table 5 * Boundary Scan Pin Configuration and Functionality Checked BST input; must be terminated to logical HIGH or LOW to avoid floating BST input; may float or be tied to HIGH BST output; may float or be connected to TDI of another device Unchecked User I/O User I/O User I/O Reserve JTAG TCK TDI, TMS TDO TRST Pin and TAP Controller Reset An active reset (TRST) pin is not supported; however, MX devices contain power-on circuitry that resets the boundary scan circuitry upon power-up. Also, the TMS pin is equipped with an internal pull-up resistor. This allows the TAP controller to remain in or return to the Test-Logic-Reset state when there is no input or when a logical 1 is on the TMS pin. To reset the controller, TMS must be HIGH for at least five TCK cycles. Boundary Scan Description Language (BSDL) File Conforming to the IEEE Standard 1149.1 requires that the operation of the various JTAG components be documented. The BSDL file provides the standard format to describe the JTAG components that can be used by automatic test equipment software. The file includes the instructions that are supported, instruction bit pattern, and the boundary-scan chain order. For an in-depth discussion on BSDL files, please refer to Actel BSDL Files Format Description application note. Actel BSDL files are grouped into two categories generic and device-specific. The generic files assign all user I/Os as inouts. Device-specific files assign user I/Os as inputs, outputs or inouts. Generic files for MX devices are available on Actel's website at http://www.actel.com/techdocs/models/bsdl.html. 1 -1 2 v6.0 40MX and 42MX FPGA Families Development Tool Support The MX family of FPGAs is fully supported by both Actel's LiberoTM Integrated Design Environment and Designer FPGA Development software. Actel Libero IDE is a design management environment that streamlines the design flow. Libero IDE provides an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment. Libero IDE includes Synplify(R) for Actel from Synplicity(R), ViewDraw for Actel from Mentor Graphics, ModelSimTM HDL Simulator from Mentor Graphics(R), WaveFormer LiteTM from SynaptiCADTM, and Designer software from Actel. Refer to the Libero IDE flow (located on Actel's website) diagram for more information. Actel's Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes timing-driven place-and-route, and a world-class integrated static timing analyzer and constraints editor. With the Designer software, a user can lock his/her design pins before layout while minimally impacting the results of place-and-route. Additionally, the backannotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, Actel's integrated verification and logic analysis tool. Another tool included in the Designer software is the ACTgen macro builder, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. Actel's Designer software is compatible with the most popular FPGA design entry and verification tools from companies such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems. Actel's Designer software is compatible with the most popular FPGA design entry and verification tools from companies such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems. Related Documents Application Notes Actel BSDL Files Format Description www.actel.com/documents/BSDLformat_AN.pdf Programming Antifuse Devices http://www.actel.com/documents/ AntifuseProgram_AN.pdf Actel's Implementation of Security in Actel Antifuse FPGAs www.actel.com/documents/Antifuse_Security_AN.pdf User's Guides and Manuals Antifuse Macro Library Guide www.actel.com/documents/libguide_UG.pdf Silicon Sculptor II www.actel.com/techdocs/manuals/default.asp#programmers Miscellaneous Libero IDE Flow Diagram www.actel.com/products/tools/libero/flow.html v6.0 1-13 40MX and 42MX FPGA Families 5.0V Operating Conditions Table 6 * Symbol VCC VI VO tSTG DC Supply Voltage Input Voltage Output Voltage Storage Temperature Absolute Maximum Ratings for 40MX Devices* Parameter Limits -0.5 to +7.0 -0.5 to VCC+0.5 -0.5 to VCC+0.5 -65 to +150 Units V V V C Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. Table 7 * Symbol VCCI VCCA VI VO tSTG Absolute Maximum Ratings for 42MX Devices* Parameter DC Supply Voltage for I/Os DC Supply Voltage for Array Input Voltage Output Voltage Storage Temperature Limits -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCCI+0.5 -0.5 to VCCI+0.5 -65 to +150 Units V V V V C Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. Table 8 * Parameter Temperature Range* VCC (40MX) VCCA (42MX) VCCI (42MX) Recommended Operating Conditions Commercial 0 to +70 4.75 to 5.25 4.75 to 5.25 4.75 to 5.25 Industrial -40 to +85 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 Military -55 to +125 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 Units C V V V Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for military grades. 1 -1 4 v6.0 40MX and 42MX FPGA Families 5V TTL Electrical Specifications Table 9 * 5V TTL Electrical Specifications Commercial Symbol VOH1 VOL1 Parameter IOH = -10mA IOH = -4mA IOL = 10mA IOL = 6mA VIL VIH (40MX) VIH (42MX) IIL IIH Input Transition Time, TR and TF CIO I/O Capacitance Standby ICC2 Current, A40MX02, A40MX04 A42MX09 A42MX16 A42MX24, A42MX36 Low-Power Mode Standby Current 42MX devices only VIN = 0.5V VIN = 2.7V -0.3 2.0 2.0 0.8 VCC+0.3 VCCI+0.3 -10 -10 500 10 3 5 6 20 0.5 -0.3 2.0 2.0 0.8 VCC+0.3 VCCI+0.3 -10 -10 500 10 25 25 25 25 ICC - 5.0 -0.3 2.0 2.0 0.5 0.5 0.4 0.8 VCC+0.3 VCCI+0.3 -10 -10 500 10 10 25 25 25 ICC - 5.0 -0.3 2.0 2.0 0.4 0.8 VCC+0.3 VCCI+0.3 -10 -10 500 10 25 25 25 25 ICC - 5.0 Min. 2.4 Max. Commercial -F Min. 2.4 3.7 3.7 Max. Industrial Min. Max. Military Min. Max. Units V V V V V V V A A ns pF mA mA mA mA mA IIO, I/O source sink Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html) current Notes: 1. Only one output tested at a time. VCC/VCCI = min. 2. All outputs unloaded. All inputs = VCC/VCCI or GND. v6.0 1-15 40MX and 42MX FPGA Families 3.3V Operating Conditions Table 10 * Symbol VCC VI VO tSTG Absolute Maximum Ratings for 40MX Devices* Parameter DC Supply Voltage Input Voltage Output Voltage Storage Temperature Limits -0.5 to +7.0 -0.5 to VCC+0.5 -0.5 to VCC+0.5 -65 to +150 Units V V V C Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. Table 11 * Symbol VCCI VCCA VI VO tSTG Absolute Maximum Ratings for 42MX Devices* Parameter DC Supply Voltage for I/Os DC Supply Voltage for Array Input Voltage Output Voltage Storage Temperature Limits -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCCI+0.5 -0.5 to VCCI+0.5 -65 to +150 Units V V V V C Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. Table 12 * Parameter Temperature Range* VCC (40MX) VCCA (42MX) VCCI (42MX) Recommended Operating Conditions Commercial 0 to +70 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 Industrial -40 to +85 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 Military -55 to +125 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 Units C V V V Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for military grades. 1 -1 6 v6.0 40MX and 42MX FPGA Families 3.3V LVTTL Electrical Specifications Table 13 * 3.3V LVTTL Electrical Specifications Commercial Symbol VOH1 VOL1 VIL VIH (40MX) VIH (42MX) IIL IIH Input Transition Time, TR and TF CIO I/O Capacitance Standby Current, ICC2 A40MX02, A40MX04 A42MX09 A42MX16 A42MX24, A42MX36 Low-Power Mode Standby Current IIO, I/O current Notes: 1. Only one output tested at a time. VCC/VCCI = min. 2. All outputs unloaded. All inputs = VCC/VCCI or GND. source 42MX devices only Parameter IOH = -4mA IOL = 6mA -0.3 2.0 2.0 Min. 2.15 0.4 0.8 VCC+0.3 VCCI+0.3 -10 -10 500 10 3 5 6 15 0.5 -0.3 2.0 2.0 Max. Commercial -F Min. 2.15 0.4 0.8 VCC+0.3 VCCI+0.3 -10 -10 500 10 25 25 25 25 ICC - 5.0 -0.3 2.0 2.0 Max. Industrial Min. 2.4 0.48 0.8 VCC+0.3 VCCI+0.3 -10 -10 500 10 10 25 25 25 ICC - 5.0 -0.3 2.0 2.0 Max. Military Min. 2.4 0.48 0.8 VCC+0.3 VCCI+0.3 -10 -10 500 10 25 25 25 25 ICC - 5.0 Max. Units V V V V V A A ns pF mA mA mA mA mA sink Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html) v6.0 1-17 40MX and 42MX FPGA Families Mixed 5.0V/3.3V Operating Conditions (for 42MX Devices Only) Table 14 * Symbol VCCI VCCA VI VO tSTG Absolute Maximum Ratings* Parameter DC Supply Voltage for I/Os DC Supply Voltage for Array Input Voltage Output Voltage Storage Temperature Limits -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCCI+0.5 -0.5 to VCCI+0.5 -65 to +150 Units V V V V C Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. Table 15 * Parameter Temperature Range* VCCA VCCI Recommended Operating Conditions Commercial 0 to +70 4.75 to 5.25 3.14 to 3.47 Industrial -40 to +85 4.5 to 5.5 3.0 to 3.6 Military -55 to +125 4.5 to 5.5 3.0 to 3.6 Units C V V Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for military grades. Mixed 5.0V/3.3V Electrical Specifications Table 16 * Mixed 5.0V/3.3V Electrical Specifications Commercial Symbol VOH1 VOL1 VIL VIH IL IH Input Transition Time, TR and TF CIO I/O Capacitance Standby Current, ICC2 A42MX09 A42MX16 A42MX24, A42MX36 Low-Power Mode Standby Current IIO I/O source sink current Notes: 1. Only one output tested at a time. VCCI = min. 2. All outputs unloaded. All inputs = VCCI or GND. VIN = 0.5V VIN = 2.7V Parameter IOH = -10mA IOH = -4mA IOL = 10mA IOL = 6mA -0.3 2.0 0.8 VCCI+0.3 -10 -10 500 10 5 6 20 0.5 -0.3 2.0 0.8 VCCI+0.3 -10 -10 500 10 25 25 25 ICC - 5.0 -0.3 2.0 0.5 0.5 0.4 0.8 VCCI+0.3 -10 -10 500 10 25 25 25 ICC - 5.0 -0.3 2.0 0.4 0.8 VCCI+0.3 -10 -10 500 10 25 25 25 ICC - 5.0 Min. 2.4 Max. Commercial '-F Min. 2.4 3.7 3.7 Max. 'Industrial Min. Max. Military Min. Max. Units V V V V V V A A ns pF mA mA mA mA Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html) 1 -1 8 v6.0 40MX and 42MX FPGA Families Output Drive Characteristics for 5.0V PCI Signaling MX PCI device I/O drivers were designed specifically for high-performance PCI systems. Figure 1-16 on page 1-21 shows the typical output drive characteristics of the MX devices. MX output drivers are compliant with the PCI Local Bus Specification. Table 17 * DC Specification (5.0V PCI Signaling)1 PCI Symbol VCCI VIH VIL IIH IIL VOH VOL CIN CCLK LPIN Notes: 1. PCI Local Bus Specification, Version 2.1, Section 4.2.1.1. 2. Maximum rating for VCCI -0.5V to 7.0V. 3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance. Table 18 * AC Specifications (5.0V PCI Signaling)* PCI Symbol ICL Slew (r) Slew (f) Parameter Low Clamp Current Output Rise Slew Rate Output Fall Slew Rate Condition -5 < VIN -1 0.4V to 2.4V load 2.4V to 0.4V load Min. -25 + (VIN +1) /0.015 1 1 5 5 Max. Min. -60 1.8 2.8 MX Max. -10 2.8 4.3 Units mA V/ns V/ns Parameter Supply Voltage for I/Os Input High Voltage Input Low Voltage Input High Leakage Current Input Low Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance CLK Pin Capacitance Pin Inductance 5 VIN = 2.7V VIN=0.5V IOUT = -2 mA IOUT = -6 mA IOUT = 3 mA, 6 mA 0.55 10 12 20 2.4 3.84 -- -- -- -- 0.33 10 10 <8 nH3 V pF pF nH Condition Min. 4.75 2.0 -0.5 Max. 5.25 VCC + 0.5 0.8 70 -70 Min. 4.75 2.0 -0.3 -- -- MX Max. 5.252 VCCI + 0.3 0.8 10 -10 Units V V V A A V Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.1.2. v6.0 1-19 40MX and 42MX FPGA Families Output Drive Characteristics for 3.3V PCI Signaling Table 19 * DC Specification (3.3V PCI Signaling)1 PCI Symbol VCCI VIH VIL IIH IIL VOH VOL CIN CCLK LPIN Notes: 1. PCI Local Bus Specification, Version 2.1, Section 4.2.2.1. 2. Maximum rating for VCCI -0.5V to 7.0V. 3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance. Table 20 * AC Specifications for (3.3V PCI Signaling)* PCI Symbol ICL Slew (r) Slew (f) Parameter Low Clamp Current Output Rise Slew Rate Output Fall Slew Rate Condition -5 < VIN -1 0.2V to 0.6V load 0.6V to 0.2V load Min. -25 + (VIN +1) /0.015 1 1 4 4 Max. Min. -60 1.8 2.8 MX Max. -10 2.8 4.0 Units mA V/ns V/ns Parameter Supply Voltage for I/Os Input High Voltage Input Low Voltage Input High Leakage Current Input Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance CLK Pin Capacitance Pin Inductance 5 IOUT = -2 mA IOUT = 3 mA, 6 mA 0.9 0.1 10 12 20 VIN = 2.7V Condition Min. 3.0 0.5 -0.5 Max. 3.6 VCC + 0.5 0.8 70 -70 3.3 0.1 VCCI 10 10 <8 nH3 Min. 3.0 0.5 -0.3 MX Max. 3.6 VCCI + 0.3 0.8 10 -10 Units V V V A A V V pF pF nH Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.2.2. 1 -2 0 v6.0 40MX and 42MX FPGA Families 0.50 0.45 0.40 0.35 0.30 0.25 0.20 Current (A) 0.15 0.10 PCI I OL Maximum MX PCI I OL PCI I OL Minimum 0.05 0.00 0 1 2 3 4 5 6 -0.05 -0.10 -0.15 -0.20 PCI I OH Maximum MX PCI I OH PCI I OH Minimum Voltage Out (V) Figure 1-16 * Typical Output Drive Characteristics (Based Upon Measured Data) v6.0 1-21 40MX and 42MX FPGA Families Junction Temperature (TJ) The temperature variable in the Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because the heat generated from dynamic power consumption is usually hotter than the ambient temperature. EQ 1-1, shown below, can be used to calculate junction temperature. EQ 1-1 Junction Temperature = T + Ta(1) P = Power ja = Junction to ambient of package. ja numbers are located in the Package Thermal Characteristics table below. Package Thermal Characteristics The device junction-to-case thermal characteristic is jc, and the junction-to-ambient air characteristic is ja. The thermal characteristics for ja are shown with two different air flow rates. The maximum junction temperature is 150C. Maximum power dissipation for commercialindustrial-grade devices is a function of ja. and Where: Ta = Ambient Temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P(2) A sample calculation of the absolute maximum power dissipation allowed for a TQFP 176-pin package at commercial temperature and still air is as follow: Max. junction temp. (C) - Max. ambient temp. (C) 150C - 70C Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------- = ---------------------------------- = 2.86W 28C/W ja (C/W) The maximum power dissipation for military-grade devices is a function of jc. A sample calculation of the absolute maximum power dissipation allowed for CQFP 208-pin package at military temperature and still air is as follows: Max. junction temp. (C) - Max. ambient temp. (C) 150C - 125C Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------- = 3.97W jc (C/W) 6.3C/W Table 21 * Package Thermal Characteristics ja Plastic Packages Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Thin Plastic Quad Flat Pack Very Thin Plastic Quad Flat Pack Very Thin Plastic Quad Flat Pack Plastic Ball Grid Array Ceramic Packages Ceramic Quad Flat Pack Ceramic Quad Flat Pack 208 256 2.0 2.0 22.0 20.0 19.8 16.5 18.0 15.0 C/W C/W Pin Count 100 160 208 240 44 68 84 176 80 100 272 jc 12.0 10.0 8.0 8.5 16.0 13.0 12.0 11.0 12.0 10.0 3.0 Still Air 27.8 26.2 26.1 25.6 20.0 25.0 22.5 24.7 38.2 35.3 18.3 1.0 m/s 2.5 m/s 200 ft/min. 500 ft/min. 23.4 22.8 22.5 22.3 24.5 21.0 18.9 19.9 31.9 29.4 14.9 21.2 21.1 20.8 20.8 22.0 19.4 17.6 18.0 29.4 27.1 13.9 Units C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W 1 -2 2 v6.0 40MX and 42MX FPGA Families Timing Models Input Delay Internal Delays Predicted Routing Delays Output Delay I/O Module Logic Module tIRD1=2.09 ns tIRD4=3.64 ns tIRD8=5.73 ns tPD=1.24 ns tCO=1.24 ns tRD1=1.28 ns tRD2=1.80 ns tRD4=2.33 ns tRD8=4.93 ns I/O Module tINYL=0.62 ns t IRD2=2.59 ns tDLH=3.32 ns tENHZ=7.92 ns Array Clock tCKH=4.55 ns FMAX=180 MHz FO=128 Note: * Values are shown for 40MX `-3' speed devices at 5.0V worst-case commercial conditions. Figure 1-17 * 40MX Timing Model* Input Delays I/O Module tINYL=0.8 ns t IRD1=2.0 ns Combinatorial Logic Module D Q t PD=1.2 ns tRD1=0.7 ns tRD2=1.9 ns tRD4=1.4 ns t RD8=2.3 ns I/O Module Sequential Logic Module Combin -atoria l Logic include tSUD=0.3 ns t HD=0.00 ns tCKH=2.70 ns F MAX=296 MHz FO = 32 tLCO=5.2 ns (light loads, pad-to-pad) t tDLH=2.5 ns Internal Delays Predicted Routing Delays Output Delays I/O Module t DLH=2.5 ns G tINH=0.0 ns t INSU=0.3 ns tINGL=1.3 ns D Q tRD1=0.70 ns D Q t ENHZ=4.9 ns G tOUTH=0.00 ns t OUTSU=0.3 ns tGLH=2.6 ns Array Clocks CO=1.3 ns Notes: *Values are shown for A42MX09 `-3' at 5.0V worst-case commercial conditions. Input module predicted routing delay. Figure 1-18 * 42MX Timing Model* v6.0 1-23 40MX and 42MX FPGA Families Input Delays I/O Module tINYL=0.8 ns tIRD1=2.0 ns Internal Delays Predicted Routing Delays Output Delays I/O Module Combinatorial Logic Module D Q tPD=1.2 ns tRD1=0.7 ns t RD2=1.9 ns tRD4=1.4 ns tRD8=2.3 ns I/O Module Sequential Logic Module Combin -atoria l Logic include tSUD=0.3 ns tHD=0.00 ns t CKH=2.70 ns FMAX=296 MHz FO = 32 t LCO=5.2 ns (light loads, pad-to-pad) tCO=1.3 ns tDLH=2.5 ns G tINH=0.0 ns t INSU=0.3 ns tINGL=1.3 ns tDLH=2.5 ns D Q tRD1=0.70 ns D Q t ENHZ=4.9 ns G tOUTH=0.00 ns tOUTSU=0.3 ns tGLH=2.6 ns Array Clocks Notes: * Values are shown for A42MX36 `-3' at 5.0V worst-case commercial conditions. ** Load-dependent Figure 1-19 * 42MX Timing Model (Logic Functions Using Quadrant Clocks) Input Delays I/O Module tINPY=1.0ns tIRD1=2.0ns D G Q tINSU=0.5ns tINH=0.0ns tINGO=1.4ns Predicted Routing Delays WD [7:0] WRAD [5:0] BLKEN WEN WCLK tADSU=1.6ns tADH=0.0ns tWENSU=2.7ns tBENS=2.8ns RD [7:0] RDAD [5:0] REN RCLK tADSU=1.6ns tADH=0.0ns tRENSU=0.6ns tRCO=3.4ns tRD1=0.9ns I/O Module tDLH=2.6ns D G Q Array Clocks FMAX =167 MHz tGHL=2.9ns tLSU=0.5ns tLH=0.0ns Note: *Values are shown for A42MX36 `-3 at 5.0V worst-case commercial conditions. Figure 1-20 * 42MX Timing Model (SRAM Functions) 1 -2 4 v6.0 40MX and 42MX FPGA Families Parameter Measurement E D TRIBUFF o PAD T AC test loads (shown below) In 50% 50% VOH 1.5V PAD 1.5V VOL tDHL tDLH E 50% 50% VCCI 1.5V PAD 10% VOL tENZL tENLZ E 50% 50% VOH PAD 90% 1.5V GND tENHZ tENZH Figure 1-21 * Output Buffer Delays Load 1 (Used to measure propagation delay) Load 2 (Used to measure rising/falling edges) VC CI GND To the output under test 35 pF To the output under test R to VCCI for tPLZ/tPZL R to GND for tPHZ/tPZH R=1k 35 pF Figure 1-22 * AC Test Loads PAD INBUF Y S A B S, A or B 50% 50% Y PAD Y GND 3V 1.5V 1.5V VCCI 50% tINYH 0V 50% tINYL Y Y t PLH 50% PHL 50% 50% tPHL 50% tPLH Figure 1-23 * Input Buffer Delays Figure 1-24 * Module Delays v6.0 1-25 40MX and 42MX FPGA Families Sequential Module Timing Characteristics D E CLK PRE CLR Y (Positive Edge-Triggered) tHD D* tSUD t WCLKA tSUENA tHENA tWCLKI tA G, CLK E Q PRE, CLR tCO tRS tWASYN Note: *D represents all data functions involving A, B, and S for multiplexed flip-flops. Figure 1-25 * Flip-Flops and Latches 1 -2 6 v6.0 40MX and 42MX FPGA Families Sequential Timing Characteristics DATA PAD G CLK PAD IBDL DATA tINH G tINSU tH EXT CLK tSU EXT Figure 1-26 * Input Buffer Latches D OBDLHS G PAD D tOUTSU G tOUTH Figure 1-27 * Output Buffer Latches v6.0 1-27 40MX and 42MX FPGA Families Decode Module Timing A B C D E F G H Y A-G, H 50% Y tPHL tPLH Figure 1-28 * Decode Module Timing SRAM Timing Characteristics Write Port WRAD [5:0] BLKEN WEN WCLK WD [7:0] RAM Array 3 2x8 or 64x4 (2 56 Bits) Read Port RDAD [5:0] LEW REN RCLK RD [7:0] Figure 1-29 * SRAM Timing Characteristics Dual-Port SRAM Timing Waveforms t RCKHL WCLK t ADSU WD[7:0] WRAD[5:0] Valid t WENSU WEN t BENSU BLKEN Valid t BENH t WENH tADH t RCKHL Note: Identical timing for falling edge clock. Figure 1-30 * 42MX SRAM Write Operation 1 -2 8 v6.0 40MX and 42MX FPGA Families tCKHL RCLK tRCKHL tRENSU REN tADSU RDAD[5:0] Valid tRENH tADH tRCO tDOH RD[7:0] Old Data New Data Note: Identical timing for falling edge clock. Figure 1-31 * 42MX SRAM Synchronous Read Operation t RDADV RDAD[5:0] ADDR1 t DOH ADDR2 t RPD RD[7:0] Data 1 Data 2 Figure 1-32 * 42MX SRAM Asynchronous Read Operation--Type 1 (Read Address Controlled) WEN tWENSU tWENH WD[7:0] WRAD[5:0] BLKEN Valid tADSU WCLK tADH tRPD tDOH RD[7:0] Old Data New Data Figure 1-33 * 42MX SRAM Asynchronous Read Operation--Type 2 (Write Address Controlled) v6.0 1-29 40MX and 42MX FPGA Families Predictable Performance: Tight Delay Distributions Propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as the length of routing tracks, the number of interconnect elements, or the number of inputs increases. From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout (number of loads) driven by a module. Higher fanout usually requires some paths to have longer routing tracks. The MX FPGAs deliver a tight fanout delay distribution, which is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. Actel's patented antifuse offers a very low resistive/ capacitive interconnect. The antifuses, fabricated in 0.45 m lithography, offer nominal levels of 100 resistance and 7.0fF capacitance per antifuse. MX fanout distribution is also tight due to the low number of antifuses required for each interconnect path. The proprietary architecture limits the number of antifuses per path to a maximum of four, with 90 percent of interconnects using only two antifuses. Critical Nets and Typical Nets Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are determined by net property assignment in Actel's Designer software prior to placement and routing. Up to 6% of the nets in a design may be designated as critical. Long Tracks Some nets in the design use long tracks, which are special routing resources that span multiple rows, columns, or modules. Long tracks employ three and sometimes four antifuse connections, which increase capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, up to 6 percent of nets in a fully utilized device require long tracks. Long tracks add approximately a 3 ns to a 6 ns delay, which is represented statistically in higher fanout (FO=8) routing delays in the data sheet specifications section, shown in Table 28 on page 1-36. Timing Derating MX devices are manufactured with a CMOS process. Therefore, device performance varies according to temperature, voltage, and process changes. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature and worst-case processing. Timing Characteristics Device timing characteristics fall into three categories: family-dependent, device-dependent, and designdependent. The input and output buffer characteristics are common to all MX devices. Internal routing delays are device-dependent; actual delays are not determined until after place-and-route of the user's design is complete. Delay values may then be determined by using the Designer software utility or by performing simulation with post-layout delays. 1 -3 0 v6.0 40MX and 42MX FPGA Families Temperature and Voltage Derating Factors Table 22 * 42MX Temperature and Voltage Derating Factors (Normalized to TJ = 25C, VCCA = 5.0V) Temperature 42MX Voltage 4.50 4.75 5.00 5.25 5.50 -55C 0.93 0.88 0.85 0.84 0.83 -40C 0.95 0.90 0.87 0.86 0.85 0C 1.05 1.00 0.96 0.95 0.94 25C 1.09 1.03 1.00 0.97 0.96 70C 1.25 1.18 1.15 1.12 1.10 85C 1.29 1.22 1.18 1.14 1.13 125C 1.41 1.34 1.29 1.28 1.26 1.50 1.40 1.30 -55C 1.20 -40C 1.10 0C 25C 70C 85C 125C 4.50 4.75 5.00 Voltage (V) 5.25 5.50 1.00 0.90 0.80 0.70 0.60 Note: This derating factor applies to all routing and propagation delays. Figure 1-34 * 42MX Junction Temperature and Voltage Derating Curves (Normalized to TJ = 25C, VCCA = 5.0V) Derating Factor v6.0 1-31 40MX and 42MX FPGA Families Table 23 * 40MX Temperature and Voltage Derating Factors (Normalized to TJ = 25C, VCC = 5.0V) Temperature 40MX Voltage 4.50 4.75 5.00 5.25 5.50 -55C 0.89 0.84 0.82 0.80 0.79 -40C 0.93 0.88 0.85 0.82 0.82 0C 1.02 0.97 0.94 0.91 0.90 25C 1.09 1.03 1.00 0.97 0.96 70C 1.25 1.18 1.15 1.12 1.10 85C 1.31 1.24 1.20 1.16 1.15 125C 1.45 1.37 1.33 1.29 1.28 1.50 1.40 1.30 Factor -55C 1.20 -40C 1.10 1.00 0.90 0.80 0.70 0.60 4.50 4.75 5.00 Voltage (V) 5.25 5.50 0C 25C 70C 85C 125C Note: This derating factor applies to all routing and propagation delays. Figure 1-35 * 40MX Junction Temperature and Voltage Derating Curves (Normalized to TJ = 25C, VCC = 5.0V) 1 -3 2 Derating v6.0 40MX and 42MX FPGA Families Table 24 * 42MX Temperature and Voltage Derating Factors (Normalized to TJ = 25C, VCCA = 3.3V) Temperature 42MX Voltage 3.00 3.30 3.60 -55C 0.97 0.84 0.81 -40C 1.00 0.87 0.84 0C 1.10 0.96 0.92 25C 1.15 1.00 0.96 70C 1.32 1.15 1.10 85C 1.36 1.18 1.13 125C 1.45 1.26 1.21 1.60 1.50 1.40 1.30 Derating Factor 1.20 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0.40 3.00 3.30 Voltage (V) (V) Note: This derating factor applies to all routing and propagation delays. Figure 1-36 * 42MX Junction Temperature and Voltage Derating Curves (Normalized to TJ = 25C, VCCA = 3.3V) 55C 40C 0C 25C 70C 85C 125C 3.60 v6.0 1-33 40MX and 42MX FPGA Families Table 25 * 40MX Temperature and Voltage Derating Factors (Normalized to TJ = 25C, VCC = 3.3V) Temperature 40MX Voltage 3.00 3.30 3.60 -55C 1.08 0.86 0.83 -40C 1.12 0.89 0.85 0C 1.21 0.96 0.92 25C 1.26 1.00 0.96 70C 1.50 1.19 1.14 85C 1.64 1.30 1.25 125C 2.00 1.59 1.53 2.20 2.00 1.80 55C 40C 0C 25C 70C 85C 125C Derating Factor 1.60 1.40 1.20 1.00 0.80 0.60 3.00 3.30 3.60 Voltage (V) Note: This derating factor applies to all routing and propagation delays. Figure 1-37 * 40MX Junction Temperature and Voltage Derating Curves (Normalized to TJ = 25C, VCC = 3.3V) 1 -3 4 v6.0 40MX and 42MX FPGA Families PCI System Timing Specification Table 26 and Table 27 list the critical PCI timing parameters and the corresponding timing parameters for the MX PCI-compliant devices. Table 26 * Clock Specification for 33 MHz PCI PCI Models Actel provides synthesizable VHDL and Verilog-HDL models for a PCI Target interface, a PCI Target and Target+DMA Master interface. Contact your Actel sales representative for more details. PCI Symbol tCYC tHIGH tLOW Table 27 * Parameter CLK Cycle Time CLK High Time CLK Low Time Timing Parameters for 33 MHz PCI PCI Symbol tVAL tVAL(PTP) tON tOFF tSU tSU(PTP) tH Notes: Parameter CLK to Signal Valid--Bused Signals CLK to Signal Valid--Point-to-Point Float to Active Active to Float Input Set-Up Time to CLK--Bused Signals Input Set-Up Time to CLK--Point-to-Point Input Hold to CLK Min. 2 2 2 A42MX24 Max. - - - Min. 4.0 1.9 1.9 Max. - - - A42MX36 Min. 4.0 1.9 1.9 Max. - - - Units ns ns ns Min. 30 11 11 A42MX24 Max. 11 12 - 28 - Min. 2.0 2.0 2.0 - 1.5 1.5 0 Max. 9.0 9.0 4.0 8.31 - - - A42MX36 Min. 2.0 2.0 2.0 - 1.5 1.5 0 Max. 9.0 9.0 4.0 8.31 - - - Units ns ns ns ns ns ns ns 2 - 7 10, 12 0 2 - - 1. TOFF is system dependent. MX PCI devices have 7.4 ns turn-off time, reflection is typically an additional 10 ns. 2. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than do bussed signals. GNT# has a setup of 10; REW# has a setup of 12. v6.0 1-35 40MX and 42MX FPGA Families Timing Characteristics Table 28 * A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, VCC = 4.75V, TJ = 70C) `-3' Speed Parameter Description Logic Module Propagation Delays tPD1 tPD2 tCO tGO tRS Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays1 1.3 1.8 2.3 2.9 4.9 1.5 2.1 2.7 3.3 5.7 1.7 2.4 3.0 3.7 6.5 2.0 2.8 3.6 4.4 7.6 2.8 3.9 5.0 6.1 10.6 ns ns ns ns ns 1.2 2.7 1.2 1.2 1.2 1.4 3.1 1.4 1.4 1.4 1.6 3.5 1.6 1.6 1.6 1.9 4.1 1.9 1.9 1.9 2.7 5.7 2.7 2.7 2.7 ns ns ns ns ns `-2' Speed `-1' Speed `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Logic Module Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Logic Module Sequential Timing2 tSUD tHD3 tSUENA tHENA tWCLKA tWASYN tA fMAX Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency (FO = 128) 3.1 0.0 3.1 0.0 3.3 3.3 4.8 181 3.5 0.0 3.5 0.0 3.8 3.8 5.6 168 4.0 0.0 4.0 0.0 4.3 4.3 6.3 154 4.7 0.0 4.7 0.0 5.0 5.0 7.5 134 6.6 0.0 6.6 0.0 7.0 7.0 10.4 80 ns ns ns ns ns ns ns MHz Input Module Propagation Delays tINYH tINYL Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold time for this macro. 4. Delays based on 35pF loading. Pad-to-Y HIGH Pad-to-Y LOW 0.7 0.6 0.8 0.7 0.9 0.8 1.1 1.0 1.5 1.3 ns ns 1 -3 6 v6.0 40MX and 42MX FPGA Families Table 28 * A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCC = 4.75V, TJ = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 1 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 2.1 2.6 3.1 3.6 5.7 2.4 3.0 3.6 4.2 6.6 2.2 3.4 4.1 4.8 7.5 3.2 4.0 4.8 5.6 8.8 4.5 5.6 6.7 7.8 12.4 ns ns ns ns ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tP fMAX Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold time for this macro. 4. Delays based on 35pF loading. Input Low to HIGH Input High to LOW Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 4.7 4.8 188 181 2.2 2.4 2.2 2.4 0.4 0.5 5.4 5.6 175 168 4.6 4.6 4.8 4.8 2.6 2.7 2.6 2.7 0.5 0.6 6.1 6.3 160 154 5.3 5.3 5.6 5.6 2.9 3.1 2.9 3.01 0.5 0.7 7.2 7.5 139 134 6.0 6.0 6.3 6.3 3.4 3.6 3.4 3.6 0.6 0.8 10.0 10.4 83 80 7.0 7.0 7.4 7.4 4.8 5.1 4.8 5.1 0.8 1.2 9.8 9.8 10.4 10.4 ns ns ns ns ns ns MHz v6.0 1-37 40MX and 42MX FPGA Families Table 28 * A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCC = 4.75V, TJ = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description TTL Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data-to-Pad HIGH Data-to-Pad LOW Enable HIGH Enable LOW Pad Pad Z Z to to 4 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 3.3 4.0 3.7 4.7 7.9 5.9 0.02 0.03 3.8 4.6 4.3 5.4 9.1 6.8 0.02 0.03 4.3 5.2 4.9 6.1 10.4 7.7 0.03 0.03 5.1 6.1 5.8 7.2 12.2 9.0 0.03 0.04 7.2 8.6 8.0 10.1 17.1 12.6 0.04 0.06 ns ns ns ns ns ns ns/pF ns/pF Enable Pad HIGH to Z Enable Pad LOW to Z Delta LOW to HIGH Delta HIGH to LOW CMOS Output Module Timing4 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold time for this macro. 4. Delays based on 35pF loading. Data-to-Pad HIGH Data-to-Pad LOW Enable HIGH Enable LOW Pad Pad Z Z to to 3.9 3.4 3.4 4.9 7.9 5.9 0.03 0.02 4.5 3.9 3.9 5.6 9.1 6.8 0.04 0.02 5.1 4.4 4.4 6.4 10.4 7.7 0.04 0.03 6.05 5.2 5.2 7.5 12.2 9.0 0.05 0.03 8.5 7.3 7.3 10.5 17.0 12.6 0.07 0.04 ns ns ns ns ns ns ns/pF ns/pF Enable Pad HIGH to Z Enable Pad LOW to Z Delta LOW to HIGH Delta HIGH to LOW 1 -3 8 v6.0 40MX and 42MX FPGA Families Table 29 * A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, VCC = 3.0V, TJ = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Logic Module Propagation Delays tPD1 tPD2 tCO tGO tRS Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q 1 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 1.7 3.7 1.7 1.7 1.7 2.0 4.3 2.0 2.0 2.0 2.3 4.9 2.3 2.3 2.3 2.7 5.7 2.7 2.7 2.7 3.7 8.0 3.7 3.7 3.7 ns ns ns ns ns Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2 2.0 2.7 3.4 4.2 7.1 2.2 3.1 3.9 4.8 8.2 2.5 3.5 4.4 5.4 9.2 3.0 4.1 5.2 6.3 10.9 4.2 5.7 7.3 8.9 15.2 ns ns ns ns ns Logic Module Sequential Timing tSUD tHD3 tSUENA tHENA tWCLKA tWASYN tA fMAX Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency (FO = 128) 4.3 0.0 4.3 0.0 4.6 4.6 6.8 109 4.9 0.0 4.9 0.0 5.3 5.3 7.8 101 5.6 0.0 5.6 0.0 6.0 6.0 8.9 92 6.6 0.0 6.6 0.0 7.0 7.0 10.4 80 9.2 0.0 9.2 0.0 9.8 9.8 14.6 48 ns ns ns ns ns ns ns MHz Input Module Propagation Delays tINYH tINYL Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold time for this macro. 4. Delays based on 35 pF loading. Pad-to-Y HIGH Pad-to-Y LOW 1.0 0.9 1.1 1.0 1.3 1.1 1.5 1.3 2.1 1.9 ns ns v6.0 1-39 40MX and 42MX FPGA Families Table 29 * A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCC = 3.0V, TJ = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 1 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 2.9 3.6 4.4 5.1 8.0 3.4 4.2 5.0 5.9 9.26 3.8 4.8 5.7 6.7 10.5 4.5 5.6 6.7 7.8 12.6 6.3 7.8 9.4 11.0 17.3 ns ns ns ns ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tP fMAX Input LOW to HIGH Input HIGH to LOW Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 6.5 6.8 113 109 3.1 3.3 3.1 3.3 0.6 0.8 7.5 7.8 105 101 6.4 6.4 6.7 6.7 3.6 3.8 3.6 3.8 0.6 0.9 8.5 8.9 96 92 7.4 7.4 7.8 7.8 4.1 4.3 4.1 4.3 0.7 1.0 10.1 10.4 83 80 8.3 8.3 8.8 8.8 4.8 5.1 4.8 5.1 0.8 1.2 14.1 14.6 50 48 9.8 9.8 10.4 10.4 6.7 7.1 6.7 7.1 1.2 1.6 13.7 13.7 14.5 14.5 ns ns ns ns ns ns MHz Maximum Frequency FO = 16 FO = 128 TTL Output Module Timing4 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold time for this macro. 4. Delays based on 35 pF loading. Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z Delta LOW to HIGH Delta HIGH to LOW 4.7 5.6 5.2 6.6 11.1 8.2 0.03 0.04 5.4 6.4 6.0 7.6 12.8 9.5 0.03 0.04 6.1 7.3 6.8 8.6 14.5 10.7 0.04 0.05 7.2 8.6 8.1 10.1 17.1 12.6 0.04 0.06 10.0 12.0 11.3 14.1 23.9 17.7 0.06 0.08 ns ns ns ns ns ns ns/pF ns/pF 1 -4 0 v6.0 40MX and 42MX FPGA Families Table 29 * A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCC = 3.0V, TJ = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Notes: Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z Delta LOW to HIGH Delta HIGH to LOW 4 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 5.5 4.8 4.7 6.8 11.1 8.2 0.05 0.03 6.4 5.5 5.5 7.9 12.8 9.5 0.05 0.03 7.2 6.2 6.2 8.9 14.5 10.7 0.06 0.04 8.5 7.3 7.3 10.5 17.1 12.6 0.07 0.04 11.9 10.2 10.2 14.7 23.9 17.7 0.10 0.06 ns ns ns ns ns ns ns/pF ns/pF 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold time for this macro. 4. Delays based on 35 pF loading. v6.0 1-41 40MX and 42MX FPGA Families Table 30 * A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, VCC = 4.75V, TJ = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Logic Module Propagation Delays tPD1 tPD2 tCO tGO tRS Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q 1 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 1.2 2.3 1.2 1.2 1.2 1.4 3.1 1.4 1.4 1.4 1.6 3.5 1.6 1.6 1.6 1.9 4.1 1.9 1.9 1.9 2.7 5.7 2.7 2.7 2.7 ns ns ns ns ns Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2 1.2 1.9 2.4 2.9 5.0 1.6 2.2 2.8 3.4 5.8 1.8 2.5 3.2 3.9 6.6 2.1 2.9 3.7 4.5 7.8 3.0 4.1 5.2 6.3 10.9 ns ns ns ns ns Logic Module Sequential Timing tSUD tHD3 tSUENA tHENA tWCLKA tWASYN tA fMAX Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency (FO = 128) 3.1 0.0 3.1 0.0 3.3 3.3 4.8 181 3.5 0.0 3.5 0.0 3.8 3.8 5.6 167 4.0 0.0 4.0 0.0 4.3 4.3 6.3 154 4.7 0.0 4.7 0.0 5.0 5.0 7.5 134 6.6 0.0 6.6 0.0 7.0 7.0 10.4 80 ns ns ns ns ns ns ns MHz Input Module Propagation Delays tINYH tINYL Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to check the hold time for this macro. 4. Delays based on 35 pF loading. Pad-to-Y HIGH Pad-to-Y LOW 0.7 0.6 0.8 0.7 0.9 0.8 1.1 1.0 1.5 1.3 ns ns 1 -4 2 v6.0 40MX and 42MX FPGA Families Table 30 * A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCC = 4.75V, TJ = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 1 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 2.1 2.6 3.1 3.6 5.7 2.4 3.0 3.6 4.2 6.6 2.2 3.4 4.1 4.8 7.5 3.2 4.0 4.8 5.6 8.8 4.5 5.6 6.7 7.8 12.4 ns ns ns ns ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tP fMAX Input Low to HIGH Input High to LOW Minimum Width HIGH Minimum Width LOW FO = 16 FO = 128 FO = 16 FO = 128 2.2 2.4 2.2 2.4 0.4 0.5 4.7 4.8 188 181 5.4 5.6 175 168 4.6 4.6 4.8 4.8 2.6 2.7 2.6 2.7 0.5 0.6 6.1 6.3 160 154 5.3 5.3 5.6 5.6 2.9 3.1 2.9 3.01 0.5 0.7 7.2 7.5 139 134 6.0 6.0 6.3 6.3 3.4 3.6 3.4 3.6 0.6 0.8 10.0 10.4 83 80 7.0 7.0 7.4 7.4 4.8 5.1 4.8 5.1 0.8 1.2 9.8 9.8 10.4 10.4 ns ns ns ns ns ns MHz Pulse FO = 16 FO = 128 Pulse FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 Maximum Skew Minimum Period Maximum Frequency TTL Output Module Timing4 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to check the hold time for this macro. 4. Delays based on 35 pF loading. Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z Delta LOW to HIGH Delta HIGH to LOW 3.3 4.0 3.7 4.7 7.9 5.9 0.02 0.03 3.8 4.6 4.3 5.4 9.1 6.8 0.02 0.03 4.3 5.2 4.9 6.1 10.4 7.7 0.03 0.03 5.1 6.1 5.8 7.2 12.2 9.0 0.03 0.04 7.2 8.6 8.0 10.1 17.1 12.6 0.04 0.06 ns ns ns ns ns ns ns/pF ns/pF v6.0 1-43 40MX and 42MX FPGA Families Table 30 * A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCC = 4.75V, TJ = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Notes: Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z Delta LOW to HIGH Delta HIGH to LOW 1 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 3.9 3.4 3.4 4.9 7.9 5.9 0.03 0.02 4.5 3.9 3.9 5.6 9.1 6.8 0.04 0.02 5.1 4.4 4.4 6.4 10.4 7.7 0.04 0.03 6.05 5.2 5.2 7.5 12.2 9.0 0.05 0.03 8.5 7.3 7.3 10.5 17.0 12.6 0.07 0.04 ns ns ns ns ns ns ns/pF ns/pF 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to check the hold time for this macro. 4. Delays based on 35 pF loading. 1 -4 4 v6.0 40MX and 42MX FPGA Families Table 31 * A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, VCC = 3.0V, TJ = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Logic Module Propagation Delays tPD1 tPD2 tCO tGO tRS Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q 1 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 1.7 3.7 1.7 1.7 1.7 2.0 4.3 2.0 2.0 2.0 2.3 4.9 2.3 2.3 2.3 2.7 5.7 2.7 2.7 2.7 3.7 8.0 3.7 3.7 3.7 ns ns ns ns ns Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2 1.9 2.7 3.4 4.1 7.1 2.2 3.1 3.9 4.8 8.1 2.5 3.5 4.4 5.4 9.2 3.0 4.1 5.2 6.3 10.9 4.2 5.7 7.3 8.9 15.2 ns ns ns ns ns Logic Module Sequential Timing tSUD tHD3 tSUENA tHENA tWCLKA tWASYN tA fMAX Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency (FO = 128) 4.3 0.0 4.3 0.0 4.6 4.6 6.8 109 5.0 0.0 5.0 0.0 5.3 5.3 7.8 101 5.6 0.0 5.6 0.0 5.6 5.6 8.9 92 6.6 0.0 6.6 0.0 7.0 7.0 10.4 80 9.2 0.0 9.2 0.0 9.8 9.8 14.6 48 ns ns ns ns ns ns ns MHz Input Module Propagation Delays tINYH tINYL Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold time for this macro. 4. Delays based on 35 pF loading. Pad-to-Y HIGH Pad-to-Y LOW 1.0 0.9 1.1 1.0 1.3 1.1 1.5 1.3 2.1 1.9 ns ns v6.0 1-45 40MX and 42MX FPGA Families Table 31 * A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCC = 3.0V, TJ = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 1 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 2.9 3.6 4.4 5.1 8.0 3.3 4.2 5.0 5.9 9.3 3.8 4.8 5.7 6.7 10.5 4.5 5.6 6.7 7.8 12.4 6.3 7.8 9.4 11.0 17.2 ns ns ns ns ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tP fMAX Input LOW to HIGH Input HIGH to LOW Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 6.5 6.8 113 109 3.1 3.3 3.1 3.3 0.6 0.8 7.5 7.8 105 101 6.4 6.4 6.8 6.8 3.6 3.8 3.6 3.8 0.6 0.9 8.5 8.9 96 92 7.4 7.4 7.8 7.8 4.1 4.3 4.1 4.3 0.7 1.0 10.1 10.4 83 80 8.4 8.4 8.9 8.9 4.8 5.1 4.8 5.1 0.8 1.2 14.1 14.6 50 48 9.9 9.9 10.4 10.4 6.7 7.1 6.7 7.1 1.2 1.6 13.8 13.8 14.6 14.6 ns ns ns ns ns ns MHz Maximum Frequency FO = 16 FO = 128 TTL Output Module Timing4 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold time for this macro. 4. Delays based on 35 pF loading. Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z Delta LOW to HIGH Delta HIGH to LOW 4.7 5.6 5.2 6.6 11.1 8.2 0.03 0.04 5.4 6.4 6.0 7.6 12.8 9.5 0.03 0.04 6.1 7.3 6.9 8.6 14.5 10.7 0.04 0.05 7.2 8.6 8.1 10.1 17.1 12.6 0.04 0.06 10.0 12.0 11.3 14.1 23.9 17.7 0.06 0.08 ns ns ns ns ns ns ns/pF ns/pF 1 -4 6 v6.0 40MX and 42MX FPGA Families Table 31 * A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCC = 3.0V, TJ = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Notes: Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z Delta LOW to HIGH Delta HIGH to LOW 4 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 5.5 4.8 4.7 6.8 11.1 8.2 0.05 0.03 6.4 5.5 5.5 7.9 12.8 9.5 0.05 0.03 7.2 6.2 6.2 8.9 14.5 10.7 0.06 0.04 8.5 7.3 7.3 10.5 17.1 12.6 0.07 0.04 11.9 10.2 10.2 14.7 23.9 17.7 0.10 0.06 ns ns ns ns ns ns ns/pF ns/pF 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold time for this macro. 4. Delays based on 35 pF loading. v6.0 1-47 40MX and 42MX FPGA Families Table 32 * A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Logic Module Propagation tPD1 tCO tGO tRS Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays1 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 1.2 1.3 1.2 1.2 1.3 1.4 1.4 1.6 1.5 1.6 1.6 1.8 1.8 1.9 1.8 2.1 2.5 2.7 2.6 2.9 ns ns ns ns Logic Module Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Timing3, 4 0.3 0.0 0.4 0.0 3.4 4.5 3.5 0.0 0.3 0.0 0.3 268 0.4 0.0 0.5 0.0 3.8 4.9 3.8 0.0 0.3 0.0 0.3 244 0.4 0.0 0.5 0.0 4.3 5.6 4.3 0.0 0.4 0.0 0.4 224 0.5 0.0 0.6 0.0 5.0 6.6 5.1 0.0 0.4 0.0 0.4 195 0.7 0.0 0.8 0.0 7.0 9.2 7.1 0.0 0.6 0.0 0.6 117 ns ns ns ns ns ns ns ns ns ns ns MHz 0.7 0.9 1.2 1.4 2.3 0.8 1.0 1.3 1.5 2.6 0.9 1.2 1.5 1.7 2.9 1.0 1.4 1.7 2.0 3.4 1.4 1.9 2.4 2.9 4.8 ns ns ns ns ns Logic Module Sequential tSUD tHD tSUENA tHENA tWCLKA tWASYN tA tINH tINSU tOUTH tOUTSU fMAX Notes: Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. 1 -4 8 v6.0 40MX and 42MX FPGA Families Table 32 * A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y HIGH Pad-to-Y LOW G to Y HIGH G to Y LOW Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 1.0 0.8 1.3 1.3 1.2 0.9 1.4 1.4 1.3 1.0 1.6 1.6 1.6 1.2 1.9 1.9 2.2 1.7 2.7 2.7 ns ns ns ns Input Module Predicted Routing Delays2 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2.0 2.3 2.5 2.8 3.7 2.2 2.5 2.8 3.1 4.1 2.5 2.9 3.2 3.5 4.7 3.0 3.4 3.7 4.1 5.5 4.2 4.7 5.2 5.7 7.7 ns ns ns ns ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Input LOW to HIGH Input HIGH to LOW Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 0.0 0.0 2.3 2.2 3.4 3.7 296 268 1.2 1.3 1.2 1.3 0.3 0.3 0.0 0.0 2.6 2.4 3.7 4.1 269 244 2.4 2.7 3.5 3.9 1.4 1.5 1.4 1.5 0.3 0.3 0.0 0.0 3.0 3.3 4.0 4.5 247 224 2.7 3.0 3.9 4.3 1.5 1.7 1.5 1.7 0.4 0.4 0.0 0.0 3.5 3.9 4.7 5.2 215 195 3.0 3.4 4.4 4.9 1.8 2.0 1.8 2.0 0.5 0.5 0.0 0.0 4.9 5.5 7.8 8.6 129 117 3.6 4.0 5.2 5.7 2.5 2.7 2.5 2.7 0.6 0.6 5.0 5.5 7.3 8.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz Input Latch External FO = 32 Set-Up FO = 256 Input Latch External FO = 32 Hold FO = 256 Minimum Period FO = 32 FO = 256 Maximum Frequency FO = 32 FO = 256 v6.0 1-49 40MX and 42MX FPGA Families Table 32 * A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description TTL Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL Notes: 5 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-to-Out (Pad-toPad), 64 Clock Loading Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading Capacity Loading, LOW to HIGH Capacity Loading, HIGH to LOW 0.5 0.0 2.5 2.9 2.6 2.9 4.9 5.3 2.6 2.6 0.5 0.0 5.2 7.4 0.03 0.04 2.7 3.2 2.9 3.2 5.4 5.9 2.9 2.9 0.6 0.0 5.8 8.2 0.03 0.04 3.1 3.6 3.3 3.7 6.2 6.7 3.3 3.3 0.7 0.0 6.6 9.3 0.03 0.04 3.6 4.3 3.9 4.3 7.3 7.9 3.8 3.8 1.0 0.0 7.7 10.9 0.04 0.05 5.1 6.0 5.5 6.1 10.2 11.1 5.3 5.3 ns ns ns ns ns ns ns ns ns ns 10.8 15.3 0.06 0.07 ns ns ns/pF ns/pF 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. 1 -5 0 v6.0 40MX and 42MX FPGA Families Table 32 * A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL Notes: Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-to-Out (Pad-toPad), 64 Clock Loading Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading Capacity Loading, LOW to HIGH Capacity Loading, HIGH to LOW 5 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 2.4 2.9 2.7 2.9 4.9 5.3 4.2 4.2 0.5 0.0 5.2 7.4 0.03 0.04 0.5 0.0 2.7 3.2 2.9 3.2 5.4 5.9 4.6 4.6 0.6 0.0 5.8 8.2 0.03 0.04 3.1 3.6 3.3 3.7 6.2 6.7 5.2 5.2 0.7 0.0 6.6 9.3 0.03 0.04 3.6 4.3 3.9 4.3 7.3 7.9 6.1 6.1 1.0 0.0 7.7 10.9 0.04 0.05 5.1 6.0 5.5 6.1 10.2 11.1 8.6 8.6 ns ns ns ns ns ns ns ns ns ns 10.8 15.3 0.06 0.07 ns ns ns/pF ns/pF 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. v6.0 1-51 40MX and 42MX FPGA Families Table 33 * A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Logic Module Propagation tPD1 tCO tGO tRS Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays1 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 1.6 1.8 1.7 2.0 1.8 2.0 1.9 2.2 2.1 2.3 2.1 2.5 2.5 2.7 2.5 2.9 3.5 3.8 3.5 4.1 ns ns ns ns Logic Module Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 3, 4 1.0 1.3 1.6 1.9 3.2 1.1 1.4 1.8 2.1 3.6 1.2 1.6 2.0 2.4 4.1 1.4 1.9 2.4 2.9 4.8 2.0 2.7 3.3 4.0 6.7 ns ns ns ns ns Logic Module Sequential Timing tSUD tHD tSUENA tHENA tWCLKA tWASYN tA tINH tINSU tOUTH tOUTSU fMAX Notes: Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency 0.5 0.0 0.6 0.0 4.7 6.2 5.0 0.0 0.3 0.0 0.3 161 0.5 0.0 0.6 0.0 5.3 6.9 5.6 0.0 0.3 0.0 0.3 146 0.6 0.0 0.7 0.0 6.0 7.8 6.2 0.0 0.3 0.0 0.3 135 0.7 0.0 0.8 0.0 7.0 9.2 7.1 0.0 0.4 0.0 0.4 117 0.9 0.0 1.2 0.0 9.8 12.9 9.9 0.0 0.6 0.0 0.6 70 ns ns ns ns ns ns ns ns ns ns ns MHz 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. 1 -5 2 v6.0 40MX and 42MX FPGA Families Table 33 * A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y HIGH Pad-to-Y LOW G to Y HIGH G to Y LOW Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 1.5 1.2 1.8 1.8 1.6 1.3 2.0 2.0 1.8 1.4 2.3 2.3 2.17 1.7 2.7 2.7 3.0 2.4 3.7 3.7 ns ns ns ns Input Module Predicted Routing Delays2 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2.8 3.2 3.5 3.9 5.2 3.2 3.5 3.9 4.3 5.8 3.6 4.0 4.4 4.9 6.6 4.2 4.7 5.2 5.7 7.7 5.9 6.6 7.3 8.0 10.8 ns ns ns ns ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Input LOW to HIGH Input HIGH to LOW Minimum Width HIGH Minimum Width LOW FO = 32 FO = 256 FO = 32 FO = 256 1.7 1.9 1.7 1.9 0.4 0.4 0.0 0.0 3.3 3.7 5.6 6.1 177 161 0.0 0.0 3.7 4.1 6.2 6.8 161 146 4.1 4.5 5.0 5.4 1.9 2.1 1.9 2.1 0.5 0.5 0.0 0.0 4.2 4.6 6.7 7.4 148 135 4.5 5.0 5.5 6.0 2.1 2.3 2.1 2.3 0.5 0.5 0.0 0.0 4.9 5.5 7.8 8.5 129 117 5.1 5.6 6.2 6.8 2.5 2.7 2.5 2.7 0.6 0.6 0.0 0.0 6.9 7.6 12.9 14.2 77 70 6.0 6.7 7.3 8.0 3.5 3.8 3.5 3.8 0.9 0.9 8.4 9.3 10.2 11.2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz Pulse FO = 32 FO = 256 Pulse FO = 32 FO = 256 FO = 32 FO = 256 Maximum Skew Input Latch External FO = 32 Set-Up FO = 256 Input Latch External FO = 32 Hold FO = 256 Minimum Period Maximum Frequency FO = 32 FO = 256 FO = 32 FO = 256 v6.0 1-53 40MX and 42MX FPGA Families Table 33 * A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description TTL Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO 5 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Data-to-Pad HIGH Data-to-Pad LOW Enable HIGH Enable LOW Pad Pad Z Z to to 3.4 4.0 3.7 4.1 6.9 7.5 5.8 5.8 0.7 0.0 8.7 0.8 0.0 3.8 4.5 4.1 4.5 7.6 8.3 6.5 6.5 0.9 0.0 9.7 4.3 5.1 4.6 5.1 8.6 9.4 7.3 7.3 1.0 0.0 10.9 5.1 6.1 5.5 6.1 10.2 11.1 8.6 8.6 1.4 0.0 12.9 7.1 8.3 7.6 8.5 14.2 15.5 12.0 12.0 ns ns ns ns ns ns ns ns ns ns Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-toOut (Pad-to-Pad), 64 Clock Loading Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading Capacity Loading, LOW to HIGH Capacity Loading, HIGH to LOW 18.0 ns tACO 12.2 13.5 15.4 18.1 25.3 ns dTLH dTHL Notes: 0.00 0.09 0.00 0.10 0.00 0.10 0.10 0.10 0.01 0.10 ns/pF ns/pF 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. 1 -5 4 v6.0 40MX and 42MX FPGA Families Table 33 * A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL Notes: Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-to-Out (Pad-toPad), 64 Clock Loading Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading Capacity Loading, LOW to HIGH Capacity Loading, HIGH to LOW 5 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 3.4 4.1 3.7 4.1 6.9 7.5 5.8 5.8 0.7 0.0 8.7 12.2 0.04 0.05 0.8 0.0 3.8 4.5 4.1 4.5 7.6 8.3 6.5 6.5 0.9 0.0 9.7 13.5 0.04 0.05 5.5 4.2 4.6 5.1 8.6 9.4 7.3 7.3 1.0 0.0 10.9 15.4 0.05 0.06 6.4 5.0 5.5 6.1 10.2 11.1 8.6 8.6 1.4 0.0 12.9 18.1 0.06 0.07 9.0 7.0 7.6 8.5 14.2 15.5 12.0 12.0 ns ns ns ns ns ns ns ns ns ns 18.0 25.3 0.08 0.10 ns ns ns/pF ns/pF 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. v6.0 1-55 40MX and 42MX FPGA Families Table 34 * A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Logic Module Propagation Delays tPD1 tCO tGO tRS Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q 1 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 1.4 1.4 1.4 1.6 1.5 1.6 1.5 1.7 1.7 1.8 1.7 2.0 2.0 2.1 2.0 2.3 2.8 3.0 2.8 3.3 ns ns ns ns Logic Module Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Timing3,4 0.3 0.0 0.7 0.0 3.4 4.5 6.8 0.0 0.5 0.0 0.5 215 0.4 0.0 0.8 0.0 3.8 5.0 7.6 0.0 0.5 0.0 0.5 195 0.4 0.0 0.9 0.0 4.3 5.6 8.6 0.0 0.6 0.0 0.6 179 0.5 0.0 1.0 0.0 5.0 6.6 10.1 0.0 0.7 0.0 0.7 156 0.7 0.0 1.4 0.0 7.1 9.2 14.1 0.0 1.0 0.0 1.0 94 ns ns ns ns ns ns ns ns ns ns ns MHz 0.8 1.0 1.3 1.6 2.6 0.9 1.2 1.4 1.7 2.9 1.0 1.3 1.6 2.0 3.2 1.2 1.5 1.9 2.3 3.8 1.6 2.1 2.7 3.2 5.3 ns ns ns ns ns Logic Module Sequential tSUD tHD tSUENA tHENA tWCLKA tWASYN tA tINH tINSU tOUTH tOUTSU fMAX Notes: Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. 1 -5 6 v6.0 40MX and 42MX FPGA Families Table 34 * A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y HIGH Pad-to-Y LOW G to Y HIGH G to Y LOW Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 1.1 0.8 1.4 1.4 1.2 0.9 1.6 1.6 1.3 1.0 1.8 1.8 1.6 1.2 2.1 2.1 2.2 1.7 2.9 2.9 ns ns ns ns Input Module Predicted Routing Delays2 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 1.8 2.1 2.3 2.6 3.6 2.0 2.3 2.6 3.0 4.0 2.3 2.6 3.0 3.3 4.6 2.7 3.1 3.5 3.9 5.4 4.0 4.3 4.9 5.4 7.5 ns ns ns ns ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Input LOW to HIGH Input HIGH to LOW Minimum Width HIGH Minimum Width LOW FO = 32 FO = 384 FO = 32 FO = 384 3.2 3.7 3.2 3.7 0.3 0.3 0.0 0.0 2.8 3.2 4.2 4.6 237 215 0.0 0.0 3.1 3.5 4.67 5.1 215 195 2.6 2.9 3.8 4.5 3.5 4.1 3.5 4.1 0.4 0.4 0.0 0.0 5.5 4.0 5.1 5.6 198 179 2.9 3.2 4.2 5.0 4.0 4.6 4.0 4.6 0.4 0.4 0.0 0.0 4.1 4.7 5.8 6.4 172 156 3.3 3.6 4.8 5.6 4.7 5.4 4.7 5.4 0.5 0.5 0.0 0.0 5.7 6.6 9.7 10.7 103 94 3.9 4.3 5.6 6.6 6.6 7.6 6.6 7.6 0.7 0.7 5.4 6.0 7.8 9.2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz Pulse FO = 32 FO = 384 Pulse FO = 32 FO = 384 FO = 32 FO = 384 Maximum Skew Input Latch External FO = 32 Set-Up FO = 384 Input Latch External FO = 32 Hold FO = 384 Minimum Period Maximum Frequency FO = 32 FO = 384 FO = 32 FO = 384 v6.0 1-57 40MX and 42MX FPGA Families Table 34 * A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description TTL Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Timing5 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Clock-to-Out (Pad-toPad), 64 Clock Loading Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 5 2.5 3.0 2.7 3.0 5.4 5.0 2.9 2.9 5.7 8.0 0.03 0.04 2.8 3.3 3.0 3.3 6.0 5.6 3.2 3.2 6.3 8.9 0.03 0.04 3.2 3.7 3.4 3.8 6.8 6.3 3.6 3.6 7.1 10.1 0.03 0.04 3.7 4.4 4.0 4.4 8.0 7.4 4.3 4.3 8.4 11.9 0.04 0.05 5.2 6.1 5.6 6.2 11.2 10.4 6.0 6.0 11.9 16.7 0.06 0.07 ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH Notes: Data-to-Pad HIGH Data-to-Pad LOW 3.2 2.5 2.7 3.0 5.4 5.0 5.1 5.1 5.7 8.0 0.03 3.6 2.7 3.0 3.3 6.0 5.6 5.6 5.6 6.3 8.9 0.03 4.0 3.1 3.4 3.8 6.8 6.3 6.4 6.4 7.1 10.1 0.03 4.7 3.6 4.0 4.4 8.0 7.4 7.5 7.5 8.4 11.9 0.04 6.6 5.1 5.6 6.2 11.2 10.4 10.5 10.5 11.9 16.7 0.06 ns ns ns ns ns ns ns ns ns ns ns/pF Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Clock-to-Out (Pad-toPad), 64 Clock Loading Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading Capacitive Loading, LOW to HIGH 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. 1 -5 8 v6.0 40MX and 42MX FPGA Families Table 35 * A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V CCA = 3.0V, T J = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Delays1 1.9 2.0 1.9 2.2 Delays2 1.1 1.5 1.8 2.2 3.6 1.2 1.6 2.0 2.4 4.0 1.4 1.8 2.3 2.7 4.5 1.6 2.1 2.7 3.2 5.3 2.3 3.0 3.8 4.5 7.5 ns ns ns ns ns 2.1 2.2 2.1 2.4 2.4 2.5 2.4 2.8 2.8 3.0 2.8 3.3 4.0 4.2 4.0 4.6 ns ns ns ns Parameter Description Logic Module Propagation tPD1 tCO tGO tRS tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tHD tSUENA tHENA tWCLKA tWASYN tA tINH tINSU tOUTH tOUTSU fMAX Notes: Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Logic Module Predicted Routing FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Logic Module Sequential Timing3, 4 0.5 0.0 1.0 0.0 4.8 6.2 9.5 0.0 0.7 0.0 0.7 129 0.5 0.0 1.1 0.0 5.3 6.9 10.6 0.0 0.8 0.0 0.8 117 0.6 0.0 1.2 0.0 6.0 7.9 12.0 0.0 0.9 0.0 0.89 108 0.7 0.0 1.4 0.0 7.1 9.2 14.1 0.0 1.01 0.0 1.01 94 0.9 0.0 2.0 0.0 9.9 12.9 19.8 0.0 1.4 0.0 1.4 56 ns ns ns ns ns ns ns ns ns ns ns MHz Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency 1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. v6.0 1-59 40MX and 42MX FPGA Families Table 35 * A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V CCA = 3.0V, T J = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Notes: Pad-to-Y HIGH Pad-to-Y LOW G to Y HIGH G to Y LOW Delays2 1.5 1.1 2.0 2.0 1.6 1.3 2.2 2.2 1.9 1.4 2.5 2.5 2.2 1.7 2.9 2.9 3.1 2.4 4.1 4.1 ns ns ns ns Input Module Predicted Routing FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2.6 2.9 3.3 3.6 5.1 2.9 3.2 3.6 4.0 5.6 3.2 3.7 4.1 4.6 6.4 3.8 4.3 4.9 5.4 7.5 5.3 6.1 6.8 7.6 10.5 ns ns ns ns ns Global Clock Network Input LOW to HIGH Input HIGH to LOW Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 0.0 0.0 3.9 4.5 7.0 7.7 142 129 5.7 6.6 5.3 6.2 0.5 2.2 0.0 0.0 4.3 4.9 7.8 8.6 129 117 4.4 4.8 5.3 6.2 6.3 7.4 5.9 6.9 0.5 2.4 0.0 0.0 4.9 5.6 8.4 9.3 119 108 4.8 5.3 5.9 6.9 7.1 8.3 6.7 7.9 0.6 2.7 0.0 0.0 5.7 6.6 9.7 10.7 103 94 5.5 6.0 6.7 7.9 8.4 9.8 7.8 9.2 0.7 3.2 0.0 0.0 8.0 9.2 16.2 17.8 62 56 6.5 7.1 7.8 9.2 11.8 13.7 11.0 12.9 1.0 4.5 9.0 9.9 11.0 12.9 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz Input Latch External FO = 32 Set-Up FO = 384 Input Latch External FO = 32 Hold FO = 384 Minimum Period FO = 32 FO = 384 Maximum Frequency FO = 32 FO = 384 1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. 1 -6 0 v6.0 40MX and 42MX FPGA Families Table 35 * A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V CCA = 3.0V, T J = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Parameter Description TTL Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Notes: Timing5 Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Clock-to-Out (Pad-toPad), 64 Clock Loading Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 3.5 4.1 3.8 4.2 7.6 7.0 4.8 4.8 8.0 11.3 0.04 0.05 3.9 4.6 4.2 4.6 8.4 7.8 5.3 5.3 8.9 12.5 0.04 0.05 4.4 5.2 4.8 5.3 9.5 8.8 6.0 6.0 10.1 14.2 0.05 0.06 5.2 6.1 5.6 6.2 11.2 10.4 7.2 7.2 11.9 16.7 0.06 0.07 7.3 8.6 7.8 8.7 15.7 14.5 10.0 10.0 16.7 23.3 0.08 0.10 ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF CMOS Output Module Timing5 Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Clock-to-Out (Pad-toPad), 64 Clock Loading Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 4.5 3.4 3.8 4.2 7.6 7.0 7.1 7.1 8.0 11.3 0.04 0.05 5.0 3.8 4.2 4.6 8.4 7.8 7.9 7.9 8.9 12.5 0.04 0.05 5.6 4.3 4.8 5.3 9.5 8.8 8.9 8.9 10.1 14.2 0.05 0.06 6.6 5.1 5.6 6.2 11.2 10.4 10.5 10.5 11.9 16.7 0.06 0.07 9.3 7.1 7.8 8.7 15.7 14.5 14.7 14.7 16.7 23.3 0.08 0.10 ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF 1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. v6.0 1-61 40MX and 42MX FPGA Families Table 36 * A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70C) `-3' Speed `-2'Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Logic Module Combinatorial tPD tPDD Functions1 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Internal Array Module Delay Internal Decode Module Delay 2 1.2 1.4 1.3 1.6 1.5 1.8 1.8 2.1 2.5 3.0 ns ns Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 0.8 1.0 1.3 1.5 2.4 0.9 1.2 1.4 1.7 2.7 1.0 1.3 1.6 1.9 3.0 1.2 1.5 1.9 2.2 3.6 1.7 2.1 2.6 3.1 5.0 ns ns ns ns ns Logic Module Sequential Timing3, 4 tCO tGO tSUD tHD tRO tSUENA tHENA tWCLKA tWASYN Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 0.4 0.0 3.3 4.4 0.3 0.0 1.4 0.5 0.0 3.7 4.8 1.3 1.2 0.4 0.0 1.6 0.5 0.0 4.2 5.3 1.4 1.3 0.4 0.0 1.8 0.6 0.0 4.9 6.5 1.6 1.5 0.5 0.0 2.1 0.8 0.0 6.9 9.0 ns 1.9 1.8 0.7 0.0 2.9 2.7 2.5 ns ns ns ns ns ns ns ns Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 0.0 0.5 4.7 1.0 1.3 0.0 0.5 5.2 1.1 1.4 0.0 0.6 5.9 1.3 1.6 0.0 0.7 6.9 1.5 1.9 0.0 1.0 9.7 2.1 2.6 ns ns ns ns ns 1 -6 2 v6.0 40MX and 42MX FPGA Families Table 36 * A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70C) `-3' Speed `-2'Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 1.8 2.1 2.3 2.5 3.4 2.0 2.3 2.5 2.8 3.8 2.3 2.6 2.9 3.2 4.3 2.7 3.1 3.4 3.7 5.1 3.8 4.3 4.8 5.2 7.1 ns ns ns ns ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Input LOW to HIGH Input HIGH to LOW Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 0.0 0.0 2.8 3.3 4.7 5.1 2.2 2.4 2.2 2.4 0.5 0.5 0.0 0.0 3.1 3.7 5.2 5.7 2.6 2.9 3.7 4.3 2.4 2.6 2.4 2.6 0.6 0.6 0.0 0.0 3.5 4.2 5.7 6.2 2.9 3.2 4.1 4.7 2.7 3.0 2.7 3.0 0.7 0.7 0.0 0.0 4.1 4.9 6.5 7.1 3.3 3.6 4.6 5.4 3.2 3.5 3.2 3.5 0.8 0.8 0.0 0.0 5.7 6.9 10.9 11.9 3.9 4.3 5.4 6.3 4.5 4.9 4.5 4.9 1.1 1.1 5.4 5.9 7.6 8.8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Input Latch External FO=32 Set-Up FO=486 Input Latch External FO=32 Hold FO=486 Minimum Period (1/fMAX) FO=32 FO=486 v6.0 1-63 40MX and 42MX FPGA Families Table 36 * A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70C) `-3' Speed `-2'Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description TTL Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL Notes: 5 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Output Set-Up I/O Latch Output Hold I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 0.5 0.0 2.4 2.8 2.5 2.8 5.2 4.8 2.9 2.9 0.5 0.0 5.6 10.6 0.04 0.03 2.7 3.2 2.8 3.1 5.7 5.3 3.2 3.2 0.6 0.0 6.1 11.8 0.04 0.03 3.1 3.6 3.2 3.5 6.5 6.0 3.6 3.6 0.7 0.0 6.9 13.4 0.04 0.03 3.6 4.2 3.8 4.2 7.6 7.1 4.3 4.3 1.0 0.0 8.1 15.7 0.05 0.04 5.1 5.9 5.3 5.9 10.7 9.9 6.0 6.0 ns ns ns ns ns ns ns ns ns ns 11.4 22.0 0.07 0.06 ns ns ns/pF ns/pF 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. 1 -6 4 v6.0 40MX and 42MX FPGA Families Table 36 * A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70C) `-3' Speed `-2'Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL Notes: Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-to-Out (Pad-toPad) 32 I/O Array Latch Clock-to-Out (Padto-Pad) 32 I/O Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 5 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 3.1 2.4 2.5 2.8 5.2 4.8 4.9 4.9 0.5 0.0 5.5 10.6 0.04 0.03 0.5 0.0 3.5 2.6 2.8 3.1 5.7 5.3 5.4 5.4 0.6 0.0 6.1 11.8 0.04 0.03 3.9 3.0 3.2 3.5 6.5 6.0 6.2 6.2 0.7 0.0 6.9 13.4 0.04 0.03 4.6 3.5 3.8 4.2 7.6 7.1 7.2 7.2 1.0 0.0 8.1 15.7 0.05 0.04 6.4 4.9 5.3 5.8 10.7 9.9 10.1 10.1 ns ns ns ns ns ns ns ns ns ns 11.3 22.0 0.07 0.06 ns ns ns/pF ns/pF 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. v6.0 1-65 40MX and 42MX FPGA Families Table 37 * A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V CCA = 3.0V, T J = 70C) `-3' Speed `-2'Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Logic Module Combinatorial tPD tPDD Functions1 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Internal Array Module Delay Internal Decode Module Delay 2 2.0 1.1 1.8 2.2 2.1 2.5 2.5 3.0 3.4 4.2 ns ns Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 1.7 2.0 1.1 1.5 1.8 1.3 1.6 2.0 2.3 3.7 1.4 1.8 2.2 2.6 4.2 1.7 2.1 2.6 3.1 5.0 2.3 3.0 3.7 4.3 7.0 ns ns ns ns ns Logic Module Sequential Timing3, 4 tCO tGO tSUD tHD tRO tSUENA tHENA tWCLKA tWASYN Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 0.6 0.0 4.6 6.1 0.4 0.0 2.0 0.6 0.0 5.2 6.8 2.1 3.4 0.5 0.0 2.2 0.7 0.0 5.8 7.7 2.0 1.9 0.6 0.0 2.5 0.8 0.0 6.9 9.0 2.3 2.1 0.7 0.0 2.9 1.2 0.0 9.6 12.6 ns 2.7 2.5 0.9 0.0 4.1 3.7 3.4 ns ns ns ns ns ns ns ns Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Input Data Pad-to-Y Input Latch Gate-toOutput Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 0.0 0.7 6.5 1.4 1.8 0.0 0.7 7.3 1.6 1.9 0.0 0.8 8.2 1.8 2.2 0.0 1.0 9.7 2.2 2.6 0.0 1.4 13.5 3.0 3.6 ns ns ns ns ns 1 -6 6 v6.0 40MX and 42MX FPGA Families Table 37 * A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V CCA = 3.0V, T J = 70C) `-3' Speed `-2'Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 2.6 2.9 3.2 3.5 4.8 2.9 3.2 3.6 3.9 5.3 3.2 3.6 4.0 4.4 6.1 3.8 4.3 4.8 5.2 7.1 5.3 6.0 6.6 7.3 10.0 ns ns ns ns ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT Input LOW to HIGH Input HIGH to LOW Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 0.0 0.0 3.0 3.3 3.0 3.3 0.8 0.8 0.0 0.0 4.4 4.8 5.1 6.0 3.3 3.7 3.4 3.7 0.8 0.8 0.0 0.0 4.8 5.3 5.7 6.6 3.8 4.2 3.8 4.2 1.0 1.0 0.0 0.0 5.5 6.0 6.4 7.5 4.5 4.9 4.5 4.9 1.1 1.1 0.0 0.0 6.5 7.1 7.6 8.8 6.3 6.9 6.3 6.9 1.6 1.6 9.1 10.0 10.6 12.4 ns ns ns ns ns ns ns ns ns ns ns ns Input Latch External FO=32 Set-Up FO=486 TTL Output Module Timing5 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Output Set-Up 0.7 3.4 4.0 3.6 3.9 7.2 6.7 4.8 4.8 0.7 3.8 4.4 4.0 4.4 8.0 7.5 5.3 5.3 0.8 4.3 5.0 4.5 5.0 9.1 8.5 6.0 6.0 1.0 5.0 5.9 5.3 5.8 10.7 9.9 7.2 7.2 1.4 7.1 8.3 7.4 8.2 14.9 13.9 10.0 10.0 ns ns ns ns ns ns ns ns ns v6.0 1-67 40MX and 42MX FPGA Families Table 37 * A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V CCA = 3.0V, T J = 70C) `-3' Speed `-2'Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description TTL Output Module Timing (Continued) tLH tLCO tACO dTLH dTHL I/O Latch Output Hold I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW Timing5 5 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 0.0 7.7 14.8 0.05 0.04 0.0 8.5 16.5 0.05 0.04 0.0 9.6 18.7 0.06 0.05 0.0 11.3 22.0 0.07 0.06 0.0 15.9 30.8 0.10 0.08 ns ns ns ns/pF ns/pF CMOS Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL tHEXT tP Notes: Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW Input Latch External FO=32 Hold FO=486 Minimum Period (1/fMAX) FO=32 FO=486 3.9 4.6 7.8 8.6 0.7 0.0 4.8 3.5 3.6 3.4 7.2 6.7 6.8 6.8 0.7 0.0 7.7 14.8 0.05 0.04 4.3 5.2 8.7 9.5 5.3 3.9 4.0 4.0 8.0 7.5 7.6 7.6 0.8 0.0 8.5 16.5 0.05 0.04 4.9 5.8 9.5 10.4 5.5 4.1 4.5 5.0 9.0 8.5 8.6 8.6 1.0 0.0 9.6 18.7 0.06 0.05 5.7 6.9 10.8 11.9 6.4 4.9 5.3 5.8 10.7 9.9 10.1 10.1 1.4 0.0 11.3 22.0 0.07 0.06 8.1 9.6 18.2 19.9 9.0 6.8 7.4 8.2 14.9 13.9 14.2 14.2 ns ns ns ns ns ns ns ns ns ns 15.9 30.8 0.10 0.08 ns ns ns/pF ns/pF ns ns ns ns 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. 1 -6 8 v6.0 40MX and 42MX FPGA Families Table 38 * A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Logic Module Combinatorial tPD tPDD Functions1 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Internal Array Module Delay Internal Decode Module Delay Delays2 1.3 1.6 1.5 1.8 1.7 2.0 2.0 2.4 2.7 3.3 ns ns Logic Module Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD5 tRDD FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 0.9 1.3 1.6 2.0 3.3 0.3 1.0 1.4 1.8 2.2 3.7 0.4 1.2 1.6 2.0 2.5 4.2 0.4 1.4 1.9 2.4 2.9 4.9 0.5 2.0 2.7 3.4 4.1 6.9 0.7 ns ns ns ns ns ns Decode-to-Output Routing Delay 3, 4 Logic Module Sequential Timing tCO tGO tSUD tHD tRO tSUENA tHENA tWCLKA tWASYN Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 0.7 0.0 3.3 4.4 0.3 0.0 1.3 1.3 0.3 0.0 1.6 0.8 0.0 3.7 4.8 1.4 1.4 0.4 0.0 1.7 0.9 0.0 4.2 5.5 1.6 1.6 0.5 0.0 2.0 1.0 0.0 4.9 6.4 1.9 1.9 0.7 0.0 2.3 1.4 0.0 6.9 9.0 2.7 2.7 ns ns ns ns 3.2 ns ns ns ns ns Synchronous SRAM Operations tRC tWC tRCKHL tRCO tADSU Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Read Cycle Time Write Cycle Time Clock HIGH/LOW Time Data Valid After Clock HIGH/LOW Address/Data Set-Up Time 1.6 6.8 6.8 3.4 3.4 1.8 7.5 7.5 3.8 3.8 2.0 8.5 8.5 4.3 4.3 2.4 10.0 10.0 5.0 5.0 3.4 14.0 14.0 7.0 7.0 ns ns ns ns ns v6.0 1-69 40MX and 42MX FPGA Families Table 38 * A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Synchronous SRAM Operations (Continued) tADH tRENSU tRENH tWENSU tWENH tBENS tBENH Address/Data Hold Time Read Enable Set-Up Read Enable Hold Write Enable Set-Up Write Enable Hold Block Enable Set-Up Block Enable Hold 0.0 0.6 3.4 2.7 0.0 2.8 0.0 0.0 0.7 3.8 3.0 0.0 3.1 0.0 0.0 0.8 4.3 3.4 0.0 3.5 0.0 0.0 0.9 5.0 4.0 0.0 4.1 0.0 0.0 1.3 7.0 5.6 0.0 5.7 0.0 ns ns ns ns ns ns ns Asynchronous SRAM Operations tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Asynchronous Access Time Read Address Valid Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up to Address Valid Read Enable Hold Write Enable Set-Up Write Enable Hold Data Out Hold Time 8.8 1.6 0.0 0.6 3.4 2.7 0.0 1.2 8.1 9.8 1.8 0.0 0.7 3.8 3.0 0.0 1.3 9.0 11.1 2.0 0.0 0.8 4.3 3.4 0.0 1.5 10.2 13.0 2.4 0.0 0.9 5.0 4.0 0.0 1.8 12.0 18.2 3.4 0.0 1.3 7.0 5.6 0.0 2.5 16.8 ns ns ns ns ns ns ns ns ns Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 0.0 0.5 4.7 1.0 1.4 0.0 0.5 5.2 1.1 1.6 0.0 0.6 5.9 1.3 1.8 0.0 0.7 6.9 1.5 2.1 0.0 1.0 9.7 2.1 2.9 ns ns ns ns ns 1 -7 0 v6.0 40MX and 42MX FPGA Families Table 38 * A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Delays2 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 2.0 2.3 2.6 3.0 4.3 2.2 2.6 2.9 3.3 4.8 2.5 2.9 3.3 3.8 5.5 2.9 3.4 3.9 4.4 6.4 4.1 4.8 5.5 6.2 9.0 ns ns ns ns ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Input LOW to HIGH Input HIGH to LOW Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 0.0 0.0 2.8 3.3 5.5 6.0 180 166 1.8 2.0 1.8 2.0 0.8 0.8 0.0 0.0 3.2 3.7 6.1 6.6 164 151 2.7 3.0 3.8 4.9 2.0 2.2 2.0 2.2 0.8 0.8 0.0 0.0 3.6 4.2 6.6 7.2 151 139 3.0 3.3 4.2 5.4 2.2 2.5 2.2 2.5 0.9 0.9 0.0 0.0 4.2 4.9 7.6 8.3 131 121 3.4 3.8 4.8 6.1 2.6 2.9 2.6 2.9 1.0 1.0 0.0 0.0 5.9 6.9 12.7 13.8 79 73 4.0 4.4 5.6 7.2 3.6 4.1 3.6 4.1 1.4 1.4 5.6 6.2 7.8 10.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz Input Latch External FO=32 Set-Up FO=635 Input Latch External FO=32 Hold FO=635 Minimum Period (1/fMAX) FO=32 FO=635 Maximum Datapath FO=32 Frequency FO=635 TTL Output Module Timing5 tDLH tDHL tENZH tENZL tENHZ Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z 2.6 3.0 2.7 3.0 5.3 2.8 3.3 3.0 3.3 5.8 3.2 3.7 3.3 3.7 6.6 3.8 4.4 3.9 4.3 7.8 5.3 6.2 5.5 6.1 10.9 ns ns ns ns ns v6.0 1-71 40MX and 42MX FPGA Families Table 38 * A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description TTL Output Module tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL Timing5 (Continued) Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Output Set-Up I/O Latch Output Hold I/O Latch Clock-to-Out (Pad-toPad) 32 I/O Array Latch Clock-to-Out (Padto-Pad) 32 I/O Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 0.5 0.0 4.9 2.9 2.9 0.5 0.0 5.7 7.8 0.07 0.07 5.5 3.3 3.3 0.6 0.0 6.3 8.6 0.08 0.08 6.2 3.7 3.7 0.7 0.0 7.1 9.8 0.09 0.09 7.3 4.4 4.4 1.0 0.0 8.4 11.5 0.10 0.10 10.2 6.1 6.1 ns ns ns ns ns 11.8 16.1 0.14 0.14 ns ns ns/pF ns/pF CMOS Output Module Timing5 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-to-Out (Pad-toPad) 32 I/O Array Latch Clock-to-Out (Padto-Pad) 32 I/O Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 0.5 0.0 5.7 7.8 0.07 0.07 3.5 2.5 2.7 2.9 5.3 4.9 5.0 5.0 0.5 0.0 6.3 8.6 0.08 0.08 3.9 2.7 3.0 3.3 5.8 5.5 5.6 5.6 0.6 0.0 7.1 9.8 0.09 0.09 4.5 3.1 3.3 3.7 6.6 6.2 6.3 6.3 0.7 0.0 8.4 11.5 0.10 0.10 5.2 3.6 3.9 4.3 7.8 7.3 7.5 7.5 1.0 0.0 11.8 16.1 0.14 0.14 7.3 5.1 5.5 6.1 10.9 10.2 10.4 10.4 ns ns ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF 1 -7 2 v6.0 40MX and 42MX FPGA Families Table 39 * A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V CCA = 3.0V, T J = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Logic Module Combinatorial tPD tPDD Functions1 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Internal Array Module Delay Internal Decode Module Delay Delays2 1.9 2.2 2.1 2.5 2.3 2.8 2.7 3.3 3.8 4.7 ns ns Logic Module Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD5 tRDD FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 1.3 1.8 2.3 2.8 4.6 0.5 1.5 2.0 2.5 3.1 5.2 0.5 1.7 2.3 2.8 3.5 5.8 0.6 2.0 2.7 3.4 4.1 6.9 0.7 2.7 3.7 4.7 5.7 9.6 1.0 ns ns ns ns ns ns Decode-to-Output Routing Delay 3, 4 Logic Module Sequential Timing tCO tGO tSUD tHD tRO tSUENA tHENA tWCLKA tWASYN Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 1.0 0.0 4.6 6.1 0.4 0.0 1.8 1.8 0.5 0.0 2.2 1.1 0.0 5.2 6.8 2.0 2.0 0.6 0.0 2.4 1.2 0.0 5.8 7.7 2.3 2.3 0.7 0.0 2.7 1.4 0.0 6.9 9.0 2.7 2.7 0.9 0.0 3.2 2.0 0.0 9.6 12.6 3.7 3.7 ns ns ns ns 4.5 ns ns ns ns ns Synchronous SRAM Operations tRC tWC tRCKHL tRCO tADSU Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Read Cycle Time Write Cycle Time Clock HIGH/LOW Time Data Valid After Clock HIGH/LOW Address/Data Set-Up Time 2.3 9.5 9.5 4.8 4.8 2.5 10.5 10.5 5.3 5.3 2.8 11.9 11.9 6.0 6.0 3.4 14.0 14.0 7.0 7.0 4.8 19.6 19.6 9.8 9.8 ns ns ns ns ns v6.0 1-73 40MX and 42MX FPGA Families Table 39 * A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V CCA = 3.0V, T J = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Synchronous SRAM Operations (Continued) tADH tRENSU tRENH tWENSU tWENH tBENS tBENH Address/Data Hold Time Read Enable Set-Up Read Enable Hold Write Enable Set-Up Write Enable Hold Block Enable Set-Up Block Enable Hold 0.0 0.9 4.8 3.8 0.0 3.9 0.0 0.0 1.0 5.3 4.2 0.0 4.3 0.0 0.0 1.1 6.0 4.8 0.0 4.9 0.0 0.0 1.3 7.0 5.6 0.0 5.7 0.0 0.0 1.8 9.8 7.8 0.0 8.0 0.0 ns ns ns ns ns ns ns Asynchronous SRAM Operations tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Asynchronous Access Time Read Address Valid Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up to Address Valid Read Enable Hold Write Enable Set-Up Write Enable Hold Data Out Hold Time 12.3 2.3 0.0 0.9 4.8 3.8 0.0 1.8 11.3 13.7 2.5 0.0 1.0 5.3 4.2 0.0 2.0 12.6 15.5 2.8 0.0 1.1 6.0 4.8 0.0 2.1 14.3 18.2 3.4 0.0 1.3 7.0 5.6 0.0 2.5 16.8 25.5 4.8 0.0 1.8 9.8 7.8 0.0 3.5 23.5 ns ns ns ns ns ns ns ns ns Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Input Data Pad-to-Y Input Latch Gate-toOutput Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 0.0 0.7 6.5 1.4 2.0 0.0 0.7 7.3 1.6 2.2 0.0 0.8 8.2 1.8 2.5 0.0 1.0 9.7 2.1 2.9 0.0 1.4 13.5 3.0 4.1 ns ns ns ns ns 1 -7 4 v6.0 40MX and 42MX FPGA Families Table 39 * A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V CCA = 3.0V, T J = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Delays2 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 2.8 3.2 3.7 4.2 6.1 3.1 3.5 4.1 4.6 6.8 3.5 4.1 4.7 5.3 7.7 4.1 4.8 5.5 6.2 9.0 5.7 6.7 7.7 8.7 12.6 ns ns ns ns ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Input LOW to HIGH Input HIGH to LOW Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period (1/fMAX) FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 0.0 0.0 4.0 4.6 9.2 9.9 108 100 2.5 2.8 2.5 2.8 1.0 1.0 0.0 0.0 4.4 5.2 10.2 11.0 98 91 4.6 5.0 5.3 6.8 2.7 3.1 2.7 3.1 1.2 1.2 0.0 0.0 5.0 5.9 11.1 12.0 90 83 5.1 5.6 5.9 7.6 3.1 3.5 3.1 3.5 1.3 1.3 0.0 0.0 5.9 6.9 12.7 13.8 79 73 5.7 6.3 6.7 8.6 3.6 4.1 3.6 4.1 1.5 1.5 0.0 0.0 8.2 9.6 21.2 23.0 47 44 6.7 7.4 7.8 10.1 5.1 5.7 5.1 5.7 2.2 2.2 9.3 10.3 11.0 14.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz Maximum Datapath FO=32 Frequency FO=635 TTL Output Module Timing5 tDLH tDHL tENZH tENZL tENHZ Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z 3.6 4.2 3.7 4.1 7.34 4.0 4.6 4.2 4.6 8.2 4.5 5.2 4.7 5.2 9.3 5.3 6.2 5.5 6.1 10.9 7.4 8.6 7.7 8.5 15.3 ns ns ns ns ns v6.0 1-75 40MX and 42MX FPGA Families Table 39 * A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V CCA = 3.0V, T J = 70C) `-3' Speed `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description TTL Output Module tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL Timing5 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Output Set-Up I/O Latch Output Hold I/O Latch Clock-to-Out (Pad-toPad) 32 I/O Array Latch Clock-to-Out (Padto-Pad) 32 I/O Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 0.7 0.0 6.9 4.9 4.9 0.7 0.0 7.9 10.9 0.10 0.10 7.6 5.5 5.5 0.8 0.0 8.8 12.1 0.11 0.11 8.7 6.2 6.2 1.0 0.0 10.0 13.7 0.12 0.12 10.2 7.3 7.3 1.4 0.0 11.8 16.1 0.14 0.14 14.3 10.2 10.2 ns ns ns ns ns 16.5 22.5 0.20 0.20 ns ns ns/pF ns/pF CMOS Output Module Timing5 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-to-Out (Pad-toPad) 32 I/O 0.7 0.0 7.9 4.9 3.4 3.7 4.1 7.4 6.9 7.0 7.0 0.7 0.0 8.8 5.5 3.8 4.1 4.6 8.2 7.6 7.8 7.8 0.8 0.0 10.0 6.2 4.3 4.7 5.2 9.3 8.7 8.9 8.9 1.0 0.0 11.8 7.3 5.1 5.5 6.1 10.9 10.2 10.4 10.4 1.4 0.0 16.5 10.3 7.1 7.7 8.5 15.3 14.3 14.6 14.6 ns ns ns ns ns ns ns ns ns ns ns 1 -7 6 v6.0 40MX and 42MX FPGA Families Pin Descriptions CLK/A/B, I/O Global Clock PRA, I/O PRB, I/O Probe A/B Clock inputs for clock distribution networks. CLK is for 40MX while CLKA and CLKB are for 42MX devices. The clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. DCLK, I/O Diagnostic Clock Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. GND Ground The Probe pin is used to output data from any userdefined design node within the device. Each diagnostic pin can be used in conjunction with the other probe pin to allow real-time diagnostic output of any signal path within the device. The Probe pin can be used as a userdefined I/O when verification has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. The Probe pin is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. QCLKA/B/C/D, I/O Quadrant Clock Input LOW supply voltage. I/O Input/Output Input, output, tristate or bi-directional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Unused I/Os pins are configured by the Designer software as shown in Table 40. Table 40 * Device A40MX02, A40MX04 A42MX09, A42MX16 A42MX24, A42MX36 Configuration of Unused I/Os Configuration Pulled LOW Pulled LOW Tristated Quadrant clock inputs for A42MX36 devices. When not used as a register control signal, these pins can function as user I/Os. SDI, I/O Serial Data Input Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. SDO, I/O Serial Data Output Serial data output for diagnostic probe and device programming. SDO is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. SDO is available for 42MX devices only. When Silicon Explorer II is being used, SDO will act as an output while the "checksum" command is run. It will return to user I/O when "checksum" is complete. TCK, I/O Test Clock In all cases, it is recommended to tie all unused MX I/O pins to LOW on the board. This applies to all dualpurpose pins when configured as I/Os as well. LP Low Power Mode Controls the low power mode of all 42MX devices. The device is placed in the low power mode by connecting the LP pin to logic HIGH. In low power mode, all I/Os are tristated, all input buffers are turned OFF, and the core of the device is turned OFF. To exit the low power mode, the LP pin must be set LOW. The device enters the low power mode 800ns after the LP pin is driven to a logic HIGH. It will resume normal operation in 200s after the LP pin is driven to a logic LOW. MODE Mode Clock signal to shift the Boundary Scan Test (BST) data into the device. This pin functions as an I/O when "Reserve JTAG" is not checked in the Designer Software. BST pins are only available in A42MX24 and A42MX36 devices. TDI, I/O Test Data In Controls the use of multifunction pins (DCLK, PRA, PRB, SDI, TDO). The MODE pin is held HIGH to provide verification capability. The MODE pin should be terminated to GND through a 10k resistor so that the MODE pin can be pulled HIGH when required. NC No Connection Serial data input for BST instructions and data. Data is shifted in on the rising edge of TCK. This pin functions as an I/O when "Reserve JTAG" is not checked in the Designer Software. BST pins are only available in A42MX24 and A42MX36 devices. TDO, I/O Test Data Out Serial data output for BST instructions and test data. This pin functions as an I/O when "Reserve JTAG" is not checked in the Designer Software. BST pins are only available in A42MX24 and A42MX36 devices. This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. v6.0 1-77 40MX and 42MX FPGA Families TMS, I/O Test Mode Select VCC Supply Voltage The TMS pin controls the use of the IEEE 1149.1 Boundary Scan pins (TCK, TDI, TDO). In flexible mode when the TMS pin is set LOW, the TCK, TDI and TDO pins are boundary scan pins. Once the boundary scan pins are in test mode, they will remain in that mode until the internal boundary scan state machine reaches the "logic reset" state. At this point, the boundary scan pins will be released and will function as regular I/O pins. The "logic reset" state is reached 5 TCK cycles after the TMS pin is set HIGH. In dedicated test mode, TMS functions as specified in the IEEE 1149.1 specifications. IEEE JTAG specification recommends a 10k pull-up resistor on the pin. BST pins are only available in A42MX24 and A42MX36 devices. Input supply voltage for 40MX devices VCCA Supply Voltage Supply voltage for array in 42MX devices VCCI Supply Voltage Supply voltage for I/Os in 42MX devices WD, I/O Wide Decode Output When a wide decode module is used in a 42MX device this pin can be used as a dedicated output from the wide decode module. This direct connection eliminates additional interconnect delays associated with regular logic modules. To implement the direct I/O connection, connect an output buffer of any type to the output of the wide decode macro and place this output on one of the reserved WD pins. 1 -7 8 v6.0 40MX and 42MX FPGA Families Package Pin Assignments 44-Pin PLCC 1 44 44-Pin PLCC Figure 2-1 * 44-Pin PLCC 44-pin PLCC Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A40MX02 Function A40MX04 Function I/O I/O VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VCC I/O VCC I/O I/O I/O I/O GND I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VCC I/O VCC I/O I/O I/O I/O GND I/O Pin Number 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-pin PLCC A40MX02 Function A40MX04 Function I/O I/O VCC I/O I/O I/O I/O I/O I/O GND CLK, I/O MODE VCC SDI, I/O DCLK, I/O PRA, I/O PRB, I/O I/O I/O I/O GND I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND CLK, I/O MODE VCC SDI, I/O DCLK, I/O PRA, I/O PRB, I/O I/O I/O I/O GND I/O v6.0 2-1 40MX and 42MX FPGA Families 68-Pin PLCC 1 68 68-Pin PLCC Figure 2-2 * 68-Pin PLCC 44-pin PLCC Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 A40MX02 Function I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O VCC I/O I/O A40MX04 Function I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O VCC I/O I/O Pin Number 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 44-pin PLCC A40MX02 Function I/O VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O A40MX04 Function I/O VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O Pin Number 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 44-pin PLCC A40MX02 Function I/O I/O GND I/O I/O CLK, I/O I/O MODE VCC SDI, I/O DCLK, I/O PRA, I/O PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O A40MX04 Function I/O I/O GND I/O I/O CLK, I/O I/O MODE VCC SDI, I/O DCLK, I/O PRA, I/O PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O 2 -2 v6.0 40MX and 42MX FPGA Families 84-Pin PLCC 1 84 84-Pin PLCC Figure 2-3 * 84-Pin PLCC v6.0 2-3 40MX and 42MX FPGA Families 84-Pin PLCC Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A40MX04 A42MX09 A42MX16 A42MX24 Function Function Function Function I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O VCC VCC I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O CLKB, I/O I/O PRB, I/O I/O GND I/O I/O I/O DCLK, I/O I/O MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O CLKB, I/O I/O PRB, I/O I/O GND I/O I/O I/O DCLK, I/O I/O MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O CLKB, I/O I/O PRB, I/O WD, I/O GND I/O WD, I/O WD, I/O DCLK, I/O I/O MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O I/O TMS, I/O TDI, I/O Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 84-Pin PLCC A40MX04 A42MX09 A42MX16 A42MX24 Function Function Function Function I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O CLK, I/O I/O MODE VCC VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O GND I/O I/O SDO, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O LP VCCA VCCI I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O GND I/O I/O SDO, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O LP VCCA VCCI I/O I/O I/O I/O GND WD, I/O I/O WD, I/O WD, I/O I/O I/O I/O VCCA WD, I/O WD, I/O WD, I/O WD, I/O I/O GND WD, I/O WD, I/O SDO, TDO, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O LP VCCA VCCI I/O I/O I/O I/O GND 2 -4 v6.0 40MX and 42MX FPGA Families 84-Pin PLCC Pin Number 71 72 73 74 75 76 77 A40MX04 A42MX09 A42MX16 A42MX24 Function Function Function Function I/O SDI, I/O DCLK, I/O PRA, I/O PRB, I/O I/O I/O I/O I/O I/O I/O I/O SDI, I/O I/O I/O I/O I/O I/O I/O SDI, I/O I/O I/O I/O I/O I/O I/O SDI, I/O I/O Pin Number 78 79 80 81 82 83 84 84-Pin PLCC A40MX04 A42MX09 A42MX16 A42MX24 Function Function Function Function I/O I/O I/O I/O GND I/O I/O I/O I/O I/O PRA, I/O I/O CLKA, I/O VCCA I/O I/O I/O PRA, I/O I/O CLKA, I/O VCCA WD, I/O WD, I/O WD, I/O PRA, I/O I/O CLKA, I/O VCCA v6.0 2-5 40MX and 42MX FPGA Families 100-Pin PQFP Package 100-Pin PQFP 100 1 Figure 2-4 * 100-Pin PQFP Package (Top View) 2 -6 v6.0 40MX and 42MX FPGA Families 100-Pin PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A40MX02 A40MX04 A42MX09 A42MX16 Function Function Function Function NC NC NC NC NC PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O NC NC NC NC NC NC NC I/O I/O NC NC NC NC NC PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O NC NC NC NC I/O I/O I/O I/O I/O I/O DCLK, I/O I/O MODE I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O DCLK, I/O I/O MODE I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCA VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 100-Pin PQFP A40MX02 A40MX04 A42MX09 A42MX16 Function Function Function Function GND GND I/O I/O I/O I/O I/O VCC VCC I/O I/O I/O NC NC NC NC NC NC NC NC VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O GND GND I/O I/O I/O I/O I/O VCC VCC I/O I/O I/O I/O I/O I/O NC NC NC NC NC VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O SDO, I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O LP VCCA VCCI VCCA I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O SDO, I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O LP VCCA VCCI VCCA I/O I/O I/O v6.0 2-7 40MX and 42MX FPGA Families 100-Pin PQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 A40MX02 A40MX04 A42MX09 A42MX16 Function Function Function Function I/O I/O I/O I/O I/O I/O NC NC NC NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O SDI, I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O I/O I/O I/O I/O SDI, I/O I/O I/O I/O I/O GND I/O Pin Number 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 100-Pin PQFP A40MX02 A40MX04 A42MX09 A42MX16 Function Function Function Function GND GND I/O I/O CLK, I/O I/O MODE VCC VCC NC NC NC SDI, I/O DCLK, I/O PRA, I/O GND GND I/O I/O CLK, I/O I/O MODE VCC VCC I/O I/O I/O SDI, I/O DCLK, I/O PRA, I/O I/O PRA, I/O I/O CLKA, I/O VCCA I/O CLKB, I/O I/O PRB, I/O I/O GND I/O I/O I/O I/O I/O PRA, I/O I/O CLKA, I/O VCCA I/O CLKB, I/O I/O PRB, I/O I/O GND I/O I/O I/O I/O 2 -8 v6.0 40MX and 42MX FPGA Families 160-Pin PQFP Package 160 1 160-Pin PQFP Figure 2-5 * 160-Pin PQFP Package (Top View) v6.0 2-9 40MX and 42MX FPGA Families 160-Pin PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A42MX09 Function I/O DCLK, I/O NC I/O I/O NC I/O I/O I/O NC GND NC I/O I/O I/O PRB, I/O I/O CLKB, I/O I/O VCCA CLKA, I/O I/O PRA, I/O NC I/O I/O I/O NC I/O GND NC I/O I/O I/O NC A42MX16 Function I/O DCLK, I/O I/O I/O I/O VCCI I/O I/O I/O I/O GND I/O I/O I/O I/O PRB, I/O I/O CLKB, I/O I/O VCCA CLKA, I/O I/O PRA, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCCI A42MX24 Function I/O DCLK, I/O I/O WD, I/O WD, I/O VCCI I/O I/O I/O I/O GND I/O WD, I/O WD, I/O I/O PRB, I/O I/O CLKB, I/O I/O VCCA CLKA, I/O I/O PRA, I/O WD, I/O WD, I/O I/O I/O I/O WD, I/O GND WD, I/O I/O I/O I/O VCCI Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 160-Pin PQFP A42MX09 Function I/O I/O SDI, I/O I/O GND I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O NC I/O NC I/O I/O VCCA VCCI GND VCCA LP I/O I/O GND I/O I/O I/O I/O GND NC A42MX16 Function I/O I/O SDI, I/O I/O GND I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCA I/O I/O VCCA VCCI GND VCCA LP I/O I/O GND I/O I/O I/O I/O GND I/O A42MX24 Function WD, I/O WD, I/O SDI, I/O I/O GND I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCA I/O I/O VCCA VCCI GND VCCA LP TCK, I/O I/O GND I/O I/O I/O I/O GND I/O 2 -1 0 v6.0 40MX and 42MX FPGA Families 160-Pin PQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 A42MX09 Function I/O I/O I/O I/O NC I/O NC I/O NC GND I/O SDO, I/O I/O I/O I/O NC I/O I/O GND NC I/O I/O I/O I/O I/O I/O I/O VCCA GND NC I/O I/O NC I/O I/O A42MX16 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O SDO, I/O I/O I/O I/O VCCI I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O I/O I/O I/O I/O I/O A42MX24 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O SDO, TDO, I/O WD, I/O WD, I/O I/O VCCI I/O WD, I/O GND I/O I/O I/O I/O I/O I/O WD, I/O I/O VCCA GND I/O I/O I/O I/O I/O I/O Pin Number 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 160-Pin PQFP A42MX09 Function I/O I/O I/O GND NC I/O I/O I/O NC I/O NC I/O I/O I/O GND I/O I/O I/O NC GND I/O I/O I/O NC GND I/O I/O I/O I/O NC I/O I/O NC VCCI GND A42MX16 Function I/O I/O I/O GND I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCA I/O I/O VCCA VCCI GND A42MX24 Function WD, I/O WD, I/O I/O GND I/O WD, I/O WD, I/O I/O VCCI WD, I/O WD, I/O I/O TDI, I/O TMS, I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCA I/O I/O VCCA VCCI GND v6.0 2-11 40MX and 42MX FPGA Families 160-Pin PQFP Pin Number 141 142 143 144 145 146 147 148 149 150 A42MX09 Function NC I/O I/O I/O GND NC I/O I/O I/O NC A42MX16 Function I/O I/O I/O I/O GND I/O I/O I/O I/O VCCA A42MX24 Function I/O I/O I/O I/O GND I/O I/O I/O I/O VCCA Pin Number 151 152 153 154 155 156 157 158 159 160 160-Pin PQFP A42MX09 Function NC NC NC NC GND I/O I/O I/O MODE GND A42MX16 Function I/O I/O I/O I/O GND I/O I/O I/O MODE GND A42MX24 Function I/O I/O I/O I/O GND I/O I/O I/O MODE GND 2 -1 2 v6.0 40MX and 42MX FPGA Families 208-Pin PQFP Package 1 208 208-Pin PQFP Figure 2-6 * 208-Pin PQFP Package (Top View) v6.0 2-13 40MX and 42MX FPGA Families 208-Pin PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A42MX16 Function GND NC MODE I/O I/O I/O I/O I/O NC NC NC I/O I/O I/O I/O NC VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCCI VCCA I/O I/O VCCA I/O I/O I/O A42MX24 Function GND VCCA MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCCI VCCA I/O I/O VCCA I/O I/O I/O A42MX36 Function GND VCCA MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCCI VCCA I/O I/O VCCA I/O I/O I/O Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 208-Pin PQFP A42MX16 Function I/O I/O I/O I/O I/O NC NC NC I/O I/O I/O I/O I/O I/O NC NC GND GND I/O I/O I/O I/O I/O I/O VCCI NC NC I/O I/O I/O I/O NC NC I/O I/O A42MX24 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND TMS, I/O TDI, I/O I/O WD, I/O WD, I/O I/O VCCI I/O I/O I/O I/O I/O WD, I/O WD, I/O I/O I/O WD, I/O A42MX36 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND TMS, I/O TDI, I/O I/O WD, I/O WD, I/O I/O VCCI I/O I/O I/O I/O QCLKA, I/O WD, I/O WD, I/O I/O I/O WD, I/O 2 -1 4 v6.0 40MX and 42MX FPGA Families 208-Pin PQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 A42MX16 Function I/O I/O I/O I/O I/O I/O I/O GND VCCA NC I/O I/O I/O I/O I/O I/O I/O I/O NC NC I/O I/O I/O I/O NC NC NC VCCI I/O I/O I/O I/O SDO, I/O I/O GND A42MX24 Function WD, I/O I/O I/O I/O I/O I/O I/O GND VCCA VCCI I/O I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O VCCI I/O WD, I/O WD, I/O I/O A42MX36 Function WD, I/O I/O I/O I/O I/O I/O I/O GND VCCA VCCI I/O I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O I/O QCLKB, I/O I/O WD, I/O WD, I/O I/O I/O I/O VCCI I/O WD, I/O WD, I/O I/O Pin Number 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 208-Pin PQFP A42MX16 Function NC I/O I/O I/O I/O I/O NC NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O LP VCCA GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O A42MX24 Function VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O TCK, I/O LP VCCA GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O A42MX36 Function VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O TCK, I/O LP VCCA GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O SDO, TDO, I/O SDO, TDO, I/O I/O GND I/O GND v6.0 2-15 40MX and 42MX FPGA Families 208-Pin PQFP Pin Number 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 A42MX16 Function NC I/O I/O I/O I/O NC NC NC NC GND I/O I/O I/O I/O I/O I/O GND I/O SDI, I/O I/O I/O I/O I/O VCCI NC NC I/O I/O I/O I/O NC I/O I/O I/O A42MX24 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O SDI, I/O I/O WD, I/O WD, I/O I/O VCCI I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O I/O I/O A42MX36 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O SDI, I/O I/O WD, I/O WD, I/O I/O VCCI I/O I/O I/O WD, I/O WD, I/O I/O QCLKD, I/O I/O I/O I/O Pin Number 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 208-Pin PQFP A42MX16 Function I/O I/O I/O PRA, I/O I/O CLKA, I/O NC NC VCCA GND I/O CLKB, I/O I/O PRB, I/O I/O I/O I/O I/O NC NC NC I/O NC I/O I/O I/O NC VCCI I/O I/O I/O I/O DCLK, I/O I/O A42MX24 Function I/O WD, I/O WD, I/O PRA, I/O I/O CLKA, I/O I/O VCCI VCCA GND I/O CLKB, I/O I/O PRB, I/O I/O WD, I/O WD, I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O I/O I/O I/O VCCI WD, I/O WD, I/O I/O I/O DCLK, I/O I/O A42MX36 Function I/O WD, I/O WD, I/O PRA, I/O I/O CLKA, I/O I/O VCCI VCCA GND I/O CLKB, I/O I/O PRB, I/O I/O WD, I/O WD, I/O I/O I/O WD, I/O WD, I/O QCLKC, I/O I/O I/O I/O I/O I/O VCCI WD, I/O WD, I/O I/O I/O DCLK, I/O I/O 2 -1 6 v6.0 40MX and 42MX FPGA Families 240-Pin PQFP Package * * * 240 1 * * * 240-Pin PQFP * * * Figure 2-7 * 240-Pin PQFP Package (Top View) * * * v6.0 2-17 40MX and 42MX FPGA Families 240-Pin PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A42MX36 Function I/O DCLK, I/O I/O I/O I/O WD, I/O WD, I/O VCCI I/O I/O I/O I/O I/O I/O QCLKC, I/O I/O WD, I/O WD, I/O I/O I/O WD, I/O WD, I/O I/O PRB, I/O I/O CLKB, I/O I/O GND VCCA VCCI I/O CLKA, I/O I/O PRA, I/O I/O 240-Pin PQFP Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 A42MX36 Function I/O WD, I/O WD, I/O I/O I/O I/O I/O I/O I/O QCLKD, I/O I/O WD, I/O WD, I/O I/O I/O I/O VCCI I/O WD, I/O WD, I/O I/O SDI, I/O I/O VCCA GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O 240-Pin PQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 A42MX36 Function VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O VCCA VCCI VCCA LP TCK, I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 240-Pin PQFP Pin Number 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 A42MX36 Function I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND GND I/O SDO, TDO, I/O I/O WD, I/O WD, I/O I/O VCCI I/O I/O I/O WD, I/O WD, I/O I/O QCLKB, I/O I/O I/O I/O I/O I/O 2 -1 8 v6.0 40MX and 42MX FPGA Families 240-Pin PQFP Pin Number 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 A42MX36 Function I/O WD, I/O WD, I/O I/O I/O I/O I/O I/O I/O VCCI VCCA GND I/O I/O I/O I/O I/O I/O WD, I/O WD, I/O I/O I/O WD, I/O WD, I/O I/O QCLKA, I/O I/O I/O I/O I/O I/O VCCI I/O WD, I/O WD, I/O 240-Pin PQFP Pin Number 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 A42MX36 Function I/O I/O TDI, I/O TMS, I/O GND VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O VCCA VCCI 240-Pin PQFP Pin Number 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 A42MX36 Function I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O GND MODE VCCA GND v6.0 2-19 40MX and 42MX FPGA Families 80-Pin VQFP 80 1 80-Pin VQFP Figure 2-8 * 80-Pin VQFP 2 -2 0 v6.0 40MX and 42MX FPGA Families 80-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 A40MX02 Function I/O NC NC NC I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O NC NC NC VCC I/O I/O I/O I/O I/O I/O GND A40MX04 Function I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND Pin Number 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 80-Pin VQFP A40MX02 Function I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O NC NC NC I/O I/O I/O GND I/O I/O CLK, I/O I/O MODE VCC NC A40MX04 Function I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O CLK, I/O I/O MODE VCC I/O Pin Number 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 80-Pin VQFP A40MX02 Function NC NC SDI, I/O DCLK, I/O PRA, I/O NC PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O A40MX04 Function I/O I/O SDI, I/O DCLK, I/O PRA, I/O NC PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O v6.0 2-21 40MX and 42MX FPGA Families 100-Pin VQFP Package 100 1 100-Pin VQFP Figure 2-9 * 100-Pin VQFP Package (Top View) 2 -2 2 v6.0 40MX and 42MX FPGA Families 100-Pin VQFP Package Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A42MX09 Function I/O MODE I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O A42MX16 Function I/O MODE I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O NC VCCI I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O 100-Pin VQFP Package Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 A42MX09 Function I/O I/O VCCA I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O SDO, I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O LP VCCA VCCI VCCA I/O I/O I/O I/O GND A42MX16 Function I/O I/O VCCA I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O SDO, I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O LP VCCA VCCI VCCA I/O I/O I/O I/O GND 100-Pin VQFP Package Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 A42MX09 Function I/O I/O I/O I/O I/O I/O SDI, I/O I/O I/O I/O I/O GND I/O I/O PRA, I/O I/O CLKA, I/O VCCA I/O CLKB, I/O I/O PRB, I/O I/O GND I/O I/O I/O I/O I/O DCLK, I/O A42MX16 Function I/O I/O I/O I/O I/O I/O SDI, I/O I/O I/O I/O I/O GND I/O I/O PRA, I/O I/O CLKA, I/O VCCA I/O CLKB, I/O I/O PRB, I/O I/O GND I/O I/O I/O I/O I/O DCLK, I/O v6.0 2-23 40MX and 42MX FPGA Families 176-Pin TQFP Package 176 1 176-Pin TQFP Figure 2-10 * 176-Pin TQFP Package (Top View) 2 -2 4 v6.0 40MX and 42MX FPGA Families 176-Pin TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A42MX09 Function GND MODE I/O I/O I/O I/O I/O NC I/O NC NC I/O NC I/O I/O I/O I/O GND NC NC I/O NC GND NC VCCA NC NC VCCI NC I/O I/O I/O NC I/O I/O A42MX16 Function GND MODE I/O I/O I/O I/O I/O NC I/O I/O I/O I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O NC I/O I/O A42MX24 Function GND MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 176-Pin TQFP A42MX09 Function I/O NC NC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O NC I/O NC NC I/O NC I/O I/O I/O NC I/O I/O NC I/O NC GND VCCA I/O I/O A42MX16 Function I/O I/O NC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA I/O I/O A42MX24 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND TMS, I/O TDI, I/O I/O WD, I/O WD, I/O I/O VCCI I/O I/O WD, I/O WD, I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O I/O I/O I/O GND VCCA WD, I/O WD, I/O v6.0 2-25 40MX and 42MX FPGA Families 176-Pin TQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 A42MX09 Function I/O I/O I/O NC I/O I/O NC NC I/O NC I/O NC I/O I/O I/O NC SDO, I/O I/O GND I/O I/O I/O I/O I/O I/O NC NC I/O I/O I/O NC I/O NC I/O I/O A42MX16 Function I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O VCCI I/O I/O I/O I/O SDO, I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O A42MX24 Function I/O I/O I/O I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O VCCI I/O WD, I/O WD, I/O I/O SDO, TDO, I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 176-Pin TQFP A42MX09 Function GND NC NC LP VCCA GND VCCI VCCA NC NC NC I/O I/O I/O I/O NC I/O I/O NC NC NC I/O I/O I/O I/O I/O I/O GND I/O SDI, I/O NC I/O I/O I/O NC A42MX16 Function GND I/O I/O LP VCCA GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O NC I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O GND I/O SDI, I/O I/O I/O I/O I/O VCCI A42MX24 Function GND I/O TCK, I/O LP VCCA GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O SDI, I/O I/O WD, I/O WD, I/O I/O VCCI 2 -2 6 v6.0 40MX and 42MX FPGA Families 176-Pin TQFP Pin Number 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 A42MX09 Function I/O I/O NC NC NC I/O NC I/O I/O I/O NC PRA, I/O I/O CLKA, I/O VCCA GND I/O CLKB, I/O A42MX16 Function I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O PRA, I/O I/O CLKA, I/O VCCA GND I/O CLKB, I/O A42MX24 Function I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O I/O WD, I/O WD, I/O PRA, I/O I/O CLKA, I/O VCCA GND I/O CLKB, I/O Pin Number 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 176-Pin TQFP A42MX09 Function I/O PRB, I/O NC I/O I/O I/O NC NC I/O NC I/O NC I/O I/O NC I/O DCLK, I/O I/O A42MX16 Function I/O PRB, I/O I/O I/O I/O I/O NC I/O I/O I/O I/O VCCI I/O I/O I/O I/O DCLK, I/O I/O A42MX24 Function I/O PRB, I/O WD, I/O WD, I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O VCCI WD, I/O WD, I/O I/O I/O DCLK, I/O I/O v6.0 2-27 40MX and 42MX FPGA Families 208-Pin CQFP ) 208207206205204203202201200 164163162161160159158157 Pin #1 Index 1 2 3 4 5 6 7 8 156 155 154 153 152 151 150 149 A42MX36 208-Pin CQFP 44 45 46 47 48 49 50 51 52 113 112 111 110 109 108 107 106 105 53 54 55 56 57 58 59 60 61 97 98 99 100101102103104 Figure 2-11 * 208-Pin CQFP (Top View) 2 -2 8 v6.0 40MX and 42MX FPGA Families 208-Pin CQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A42MX36 Function GND VCCA MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCCI VCCA I/O I/O VCCA I/O I/O I/O 208-Pin CQFP Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 A42MX36 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND TMS, I/O TDI, I/O I/O WD, I/O WD, I/O I/O VCCI I/O I/O I/O I/O QCLKA, I/O WD, I/O WD, I/O I/O I/O WD, I/O 208-Pin CQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 A42MX36 Function WD, I/O I/O I/O I/O I/O I/O I/O GND VCCA VCCI I/O I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O I/O QCLKB, I/O I/O WD, I/O WD, I/O I/O I/O I/O VCCI I/O WD, I/O WD, I/O I/O TDO, I/O I/O GND 208-Pin CQFP Pin Number 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 A42MX36 Function VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O TCK, I/O LP VCCA GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O v6.0 2-29 40MX and 42MX FPGA Families 208-Pin CQFP Pin Number 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 A42MX36 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND 208-Pin CQFP Pin Number 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 A42MX36 Function I/O SDI, I/O I/O WD, I/O WD, I/O I/O VCCI I/O I/O I/O WD, I/O WD, I/O I/O QCLKD, I/O I/O I/O I/O 208-Pin CQFP Pin Number 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 A42MX36 Function I/O WD, I/O WD, I/O PRA, I/O I/O CLKA, I/O I/O VCCI VCCA GND I/O CLKB, I/O I/O PRB, I/O I/O WD, I/O WD, I/O 208-Pin CQFP Pin Number 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 A42MX36 Function I/O I/O WD, I/O WD, I/O QCLKC, I/O I/O I/O I/O I/O I/O VCCI WD, I/O WD, I/O I/O I/O DCLK, I/O I/O 2 -3 0 v6.0 40MX and 42MX FPGA Families 256-Pin CQFP 256255254253252251250249248 200199198197196195194193 Pin #1 Index 1 2 3 4 5 6 7 8 192 191 190 189 188 187 186 185 A42MX36 256-Pin CQFP 56 57 58 59 60 61 62 63 64 137 136 135 134 133 132 131 130 129 65 66 67 68 69 70 71 72 73 121122123124125126127128 Figure 2-12 * 256-Pin CQFP (Top View) v6.0 2-31 40MX and 42MX FPGA Families 256-Pin CQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A42MX36 Function NC GND I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O VCCA VCCI GND VCCA LP TCK, I/O I/O 256-Pin CQFP Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 A42MX36 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND NC NC NC I/O SDO, TDO, I/O I/O WD, I/O WD, I/O 256-Pin CQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 A42MX36 Function I/O VCCI I/O I/O I/O WD, I/O GND WD, I/O I/O QCLKB, I/O I/O I/O I/O I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O I/O I/O I/O VCCI VCCA GND GND I/O I/O I/O I/O I/O I/O WD, I/O 256-Pin CQFP Pin Number 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 A42MX36 Function WD, I/O I/O I/O WD, I/O WD, I/O I/O QCLKA, I/O I/O GND I/O I/O I/O I/O VCCI I/O WD, I/O WD, I/O I/O I/O I/O I/O GND NC NC NC GND I/O I/O I/O I/O I/O I/O I/O GND I/O 2 -3 2 v6.0 40MX and 42MX FPGA Families 256-Pin CQFP Pin Number 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 A42MX36 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O VCCA VCCI GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O 256-Pin CQFP Pin Number 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 A42MX36 Function I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O MODE VCCA GND NC NC NC I/O DCLK, I/O I/O I/O I/O WD, I/O WD, I/O VCCI I/O I/O I/O I/O GND I/O I/O QCLKC, I/O I/O 256-Pin CQFP Pin Number 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 A42MX36 Function WD, I/O WD, I/O I/O I/O WD, I/O WD, I/O I/O PRB, I/O I/O CLKB, I/O I/O GND GND VCCA VCCI I/O CLKA, I/O I/O PRA, I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O I/O I/O I/O QCLKD, I/O I/O WD, I/O GND WD, I/O I/O 256-Pin CQFP Pin Number 246 247 248 249 250 251 252 253 254 255 256 A42MX36 Function I/O I/O VCCI I/O WD, I/O WD, I/O I/O SDI, I/O I/O GND NC v6.0 2-33 40MX and 42MX FPGA Families 272-Pin BGA Package 1 A B C D E F G H J K L M N P R T U V W Y 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 272-Pin PBGA Figure 2-13 * 272-Pin BGA Package (Top View) 2 -3 4 v6.0 40MX and 42MX FPGA Families 272-Pin PBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 A42MX36 Function GND GND I/O WD, I/O I/O I/O WD, I/O WD, I/O I/O I/O CLKA I/O I/O I/O I/O WD, I/O I/O I/O GND GND GND GND DCLK, I/O I/O I/O I/O WD, I/O I/O PRB, I/O I/O I/O WD, I/O I/O I/O WD, I/O 272-Pin PBGA Pin Number B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 A42MX36 Function I/O WD, I/O I/O GND GND I/O MODE GND I/O WD, I/O I/O QCLKC, I/O I/O I/O CLKB PRA, I/O WD, I/O I/O QCLKD, I/O I/O WD, I/O SDI, I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O VCCA WD, I/O VCCI 272-Pin PBGA Pin Number D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E17 E18 E19 E20 F1 F2 F3 F4 F17 F18 F19 F20 G1 G2 G3 G4 G17 G18 G19 G20 H1 A42MX36 Function I/O VCCI I/O VCCI I/O VCCA GND I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O VCCI VCCI I/O I/O I/O I/O 272-Pin PBGA Pin Number H2 H3 H4 H17 H18 H19 H20 J1 J2 J3 J4 J9 J10 J11 J12 J17 J18 J19 J20 K1 K2 K3 K4 K9 K10 K11 K12 K17 K18 K19 K20 L1 L2 L3 L4 A42MX36 Function I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O VCCI GND GND GND GND VCCA I/O I/O I/O I/O I/O I/O VCCI GND GND GND GND I/O VCCA VCCA LP I/O I/O VCCA VCCA v6.0 2-35 40MX and 42MX FPGA Families 272-Pin PBGA Pin Number L9 L10 L11 L12 L17 L18 L19 L20 M1 M2 M3 M4 M9 M10 M11 M12 M17 M18 M19 M20 N1 N2 N3 N4 N17 N18 N19 N20 P1 P2 P3 P4 P17 P18 P19 A42MX36 Function GND GND GND GND VCCI I/O I/O TCK, I/O I/O I/O I/O VCCI GND GND GND GND I/O I/O I/O I/O I/O I/O I/O VCCI VCCI I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O 272-Pin PBGA Pin Number P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 A42MX36 Function I/O I/O I/O I/O VCCI VCCI I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O VCCI WD, I/O I/O I/O WD, I/O VCCA VCCI I/O I/O QCLKB, I/O I/O VCCI I/O GND 272-Pin PBGA Pin Number U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 A42MX36 Function I/O I/O I/O I/O GND GND I/O I/O I/O WD, I/O I/O I/O I/O I/O WD, I/O I/O WD, I/O I/O I/O SDO, TDO, I/O I/O I/O GND GND I/O TMS, I/O I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O 272-Pin PBGA Pin Number W13 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 A42MX36 Function WD, I/O I/O I/O WD, I/O I/O WD, I/O GND GND GND GND I/O TDI, I/O WD, I/O I/O QCLKA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O WD, I/O GND GND 2 -3 6 v6.0 FPGA Families 40MX and 42MX Datasheet Information List of Changes The following table lists critical changes that were made in the current version of the document. Previous version v5.1 Changes in current version (v 6. 0 ) The "Ease of Integration" section was updated. The "Temperature Grade Offerings" section is new. The "Speed Grade Offerings" section is new. The "General Description" section was updated. The "MultiPlex I/O Modules" section was updated. The "User Security" section was updated. Table 1 * Voltage Support of MX Devices was updated. The "Power Dissipation" section was updated. The "Static Power Component" section was updated. The "Equivalent Capacitance" section was updated. Figure 1-13 * Silicon Explorer II Setup with 42MX was updated. Table 4 * Supported BST Public Instructions was updated. Figure 1-14 * 42MX IEEE 1149.1 Boundary Scan Circuitry was updated. Table 5 * Boundary Scan Pin Configuration and Functionality was updated. The "Development Tool Support" section was updated. Page 1-i 1-iii 1-iii 1-1 1-6 1-6 1-7 1-8 1-8 1-8 1-10 1-11 1-11 1-12 1-13 The Table 7 * Absolute Maximum Ratings for 42MX Devices* and the Table 6 * Absolute 1-14 Maximum Ratings for 40MX Devices* were updated. The Table 9 * 5V TTL Electrical Specifications was updated. The Table 13 * 3.3V LVTTL Electrical Specifications was updated. 1-15 1-17 In the "Mixed 5.0V/3.3V Electrical Specifications" section, Table 14 * Absolute Maximum 1-18 Ratings*, Table 15 * Recommended Operating Conditions, and Table 16 * Mixed 5.0V/3.3V Electrical Specificationswere updated. The Table 17 * DC Specification (5.0V PCI Signaling)1 was updated. The Table 19 * DC Specification (3.3V PCI Signaling) was updated. 1 1-19 1-20 The v6.0 3-1 FPGA Families 40MX and 42MX Previous version 5.1 Changes in current version (v 6. 0 ) In the 160-Pin PQFP table, the following pins changed: Pin 61 (42MX09, 42MX16, and 42MX64) has changed to LP In the 208-Pin PQFP table, the following pins changed: Pin 129 (42MX09, 42MX16, and 42MX64) has changed to LP Pin 198 (42MX09) has changed to I/O The n the 240-Pin PQFP table, the following pins changed: Pin 91 (42MX36) has changed to LP In the 100-Pin VQFP Package table, the following pins changed: Pin 62 (42MX09 and 42MX16) has changed to LP In the 176-Pin TQFP table, the following pins changed: Pin 109 (42MX09 and 42MX16) has changed to LP In the 272-Pin PBGA table, the following pins changed: Pin K20 (42MX36) has changed to LP Page 2-10 2-14 2-18 2-23 2-25 2-35 1-7 1-15 1-17 v5.0 The "Low Power Mode" section was updated. Footnote 8 in the Table 9 * 5V TTL Electrical Specifications was updated. Footnote 8 in the Table 13 * 3.3V LVTTL Electrical Specifications was updated. v4.0.1 Because the changes in this data sheet are extensive and technical in nature, this should be viewed ALL as a new document. Please read it as you would a data sheet that is published for the first time. Note that the "Package Characteristics and Mechanical Drawings" section has been eliminated from the data sheet. The mechanical drawings are now contained in a separate document, "Package Characteristics and Mechanical Drawings," available on the Actel web site. Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet Supplement." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked (production) This datasheet version contains information that is considered to be final. Datasheet Supplement The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families. 3 -2 v6.0 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Corporation 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 Actel Europe Ltd. Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone +44 (0)1276.401450 Fax +44 (0)1276.401490 Actel Japan EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 Actel Hong Kong 39th Floor, One Pacific Place 88 Queensway, Admiralty Hong Kong Phone +852.227.35712 Fax +852.227.35999 5172136-8/01.04 |
Price & Availability of A40MX02-FPQ100
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